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查看斯高帕斯 (Scopus) 概要
黃 俊達
教授
電機工程學系
https://orcid.org/0000-0001-5961-7863
h-index
h10-index
h5-index
774
引文
13
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
215
引文
8
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
42
引文
4
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1993 …
2024
每年研究成果
概覽
指紋
網路
計畫
(25)
研究成果
(103)
類似的個人檔案
(6)
指紋
查看啟用 Juinn-Dar Huang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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Keyphrases
Architectural Synthesis
16%
Area Minimization
12%
Biochip
10%
Class Encoding
8%
Communication Architecture
14%
Communication Synthesis
9%
Compliance Verification
11%
Data Transfer
9%
Design Automation
7%
Digital Microfluidic Biochips
42%
Distributed Register
14%
Distributed-register Architecture
14%
Encoding Algorithm
10%
Field Programmable Gate Arrays
19%
FPGA Technology
8%
Hardware Efficiency
10%
Integer Linear Programming
7%
Inter-island
9%
Interface Protocol
13%
Lab-on-a-chip
8%
Latency
13%
Low Power
11%
Microarchitecture
14%
Microarray Technology
11%
Microfluidic Biochip
17%
Mixing Model
10%
Multi-target
11%
Multicycle Communication
18%
Multiple Output
7%
On chip
13%
On-a-chip
7%
Performance Optimization
7%
Performance-based
11%
Popular
11%
Power Consumption
9%
Reactant Minimization
28%
Reconfigurable
14%
Register File
11%
Sample Preparation
51%
Single Electron Transistor
17%
Storage-aware
8%
Synthesis Flow
14%
Synthesis Framework
7%
System Performance
8%
Table-driven
7%
Target Concentration
17%
Technology Mapping
19%
Through Silicon via
7%
Transistor Array
16%
Wire Delay
14%
Computer Science
Architectural Synthesis
16%
Architecture Register
16%
binary decision diagram
5%
Building-Blocks
5%
Communication Architecture
14%
Computer Hardware
20%
Continuous Flow
5%
Convolutional Neural Network
17%
Criticality
7%
Deep Learning Method
7%
Design Automation
7%
Dictionary Size
5%
Encoding Algorithm
11%
Evolutionary Algorithm
5%
Experimental Result
100%
False Positive Problem
5%
Field Programmable Gate Arrays
31%
Finite-State Machine
11%
Floorplanning
5%
Functional Decomposition
5%
hard real-time
5%
Input/Output
5%
Integer-Linear Programming
13%
Interconnect Resource
7%
Learning System
8%
Machine Learning
8%
Microarchitecture
14%
Multiplexer
5%
Network Flow Model
5%
Operation Count
8%
Optimization Technique
6%
Performance Optimization
5%
Power Consumption
11%
Single Electron
17%
Space Complexity
5%
Synthesis Algorithm
10%
System on a Chip
8%
System-on-Chip
14%
Systems Performance
9%
Technology Mapping
20%
through silicon vias
7%
Time Complexity
11%
Engineering
Analog Circuit
5%
Biochemicals
14%
Convolutional Neural Network
5%
Deep Learning Method
5%
Digital Microfluidics
36%
Dilution
20%
Experimental Result
31%
Field Programmable Gate Arrays
7%
Functional Decomposition
5%
Learning System
5%
Lookup Table
8%
Microfluidic Device
5%
Mixers (Machinery)
5%
Mixture Preparation
6%
Output Function
5%
Reactant
45%
Single Electron
11%
Storage Unit
7%
System-on-Chip
5%
