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查看斯高帕斯 (Scopus) 概要
黃 俊達
教授
電子研究所
https://orcid.org/0000-0001-5961-7863
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904
引文
15
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241
引文
7
h-指數
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107
引文
5
h-指數
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1993 …
2026
每年研究成果
概覽
指紋
網路
計畫
(25)
研究成果
(111)
類似的個人檔案
(3)
指紋
查看啟用 Juinn-Dar Huang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Computer Science
Experimental Result
100%
Field Programmable Gate Arrays
27%
Transistor
20%
Technology Mapping
18%
Single Electron
17%
Convolutional Neural Network
17%
Deep Learning Method
16%
Architectural Synthesis
16%
Architecture Register
15%
Microarchitecture
14%
Communication Architecture
14%
Integer-Linear Programming
12%
Time Complexity
11%
Power Consumption
11%
Finite-State Machine
11%
System-on-Chip
10%
Synthesis Algorithm
9%
Systems Performance
8%
Encoding Algorithm
8%
Operation Count
8%
Activation Function
8%
Probability
8%
Criticality
7%
through silicon vias
7%
Interconnect Resource
7%
System on a Chip
6%
Architecture Design
6%
Input/Output
6%
Machine Learning
5%
Learning System
5%
Performance Optimization
5%
Space Complexity
5%
Dictionary Size
5%
Network Flow Model
5%
False Positive Problem
5%
Continuous Flow
5%
binary decision diagram
5%
hard real-time
5%
Floorplanning
5%
Building-Blocks
5%
Multiplexer
5%
Evolutionary Algorithm
5%
Attention (Machine Learning)
5%
Tumor Segmentation
5%
Convolutional Block Attention
5%
Nonlinear Function
5%
Model Compression
5%
Intellectual Property
5%
Processing Step
5%
Large Language Model
5%
Keyphrases
Sample Preparation
38%
Digital Microfluidic Biochips
23%
Reactant Minimization
21%
Architectural Synthesis
14%
Single Electron Transistor
14%
Transistor Array
14%
Microarchitecture
14%
Reconfigurable
14%
Target Concentration
14%
Technology Mapping
13%
Multicycle Communication
12%
Microfluidic Biochip
11%
Distributed Register
11%
Area Minimization
11%
Register File
11%
Performance-based
11%
Low Power
11%
Distributed-register Architecture
11%
Wire Delay
10%
Field Programmable Gate Array
10%
Multi-target
9%
Inter-island
9%
Mixing Model
9%
Data Transfer
8%
Latency
8%
Communication Architecture
8%
Power Consumption
8%
On chip
8%
Microarray Technology
8%
Performance Optimization
7%
Hardware Efficiency
7%
Synthesis Flow
7%
Flow-based Microfluidic Biochips
7%
Popular
6%
Table-driven
6%
Synthesis Framework
6%
System Performance
6%
Communication Synthesis
6%
Interface Protocol
6%
Chip-based
6%
Synthesis Algorithm
6%
Compliance Verification
5%
Lab-on-a-chip
5%
Fabrication Constraints
5%
Set Selection
5%
Multiplexer Tree
5%
Dictionary Size
5%
Programmable Microfluidic Device
5%
Softmax
5%
Fault Dictionary
5%
