每年專案
個人檔案
研究專長
電子設計自動化、生物晶片設計自動化、微處理器設計、矽智財與系統單晶片設計
經歷
1998/07~2003/10 創意電子公司經理
2003/11~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, 電子工程, National Chiao Tung University
外部位置
指紋
查看啟用 Juinn-Dar Huang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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過去五年中的合作和熱門研究領域
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料，或
專案
- 25 已完成
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
Huang, J.-D. (PI)
1/08/24 → 31/07/25
研究計畫: Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
Huang, J.-D. (PI)
1/08/23 → 31/07/24
研究計畫: Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
Huang, J.-D. (PI)
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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通用於深度學習之神經網路加速器晶片開發暨產業落地(1/4)
Huang, J.-D. (PI)
1/05/22 → 30/04/23
研究計畫: Other Government Ministry Institute
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智慧終端系統晶片研發與新創事業計畫-子計畫三：智慧終端晶片設計與驗證方法論之開發(2/2)
Huang, J.-D. (PI)
1/05/21 → 31/07/22
研究計畫: Other Government Ministry Institute
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An Accurate and Compact Design Integrating Seven Common Nonlinear Functions in Deep Learning
Wu, J. E., Hu, T. W., Liang, C. Y. & Huang, J. D., 2025, ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).研究成果: Conference contribution › 同行評審
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Codeword Decomposition and Recoding Based Lossless Model Compression Algorithm and Its VLSI Decompressor Design
Ho, L. M., Liang, C. Y. & Huang, J. D., 2025, AICAS 2025 - 2025 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., (AICAS 2025 - 2025 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceedings).研究成果: Conference contribution › 同行評審
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A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications
Hsieh, M. H., Li, X. H., Huang, Y. H., Kuo, P. H. & Huang, J. D., 2024, ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).研究成果: Conference contribution › 同行評審
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A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems
Chu, Y. D., Kuo, P. H., Ho, L. M. & Huang, J. D., 2024, 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 437-441 5 p. (2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings).研究成果: Conference contribution › 同行評審
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Diabetic foot ulcers segmentation challenge report: Benchmark and analysis
Yap, M. H., Cassidy, B., Byra, M., Liao, T. Y., Yi, H., Galdran, A., Chen, Y. H., Brüngel, R., Koitka, S., Friedrich, C. M., Lo, Y. W., Yang, C. H., Li, K., Lao, Q., Ballester, M. A. G., Carneiro, G., Ju, Y. J., Huang, J. D., Pappachan, J. M. & Reeves, N. D. 及其他3, , 5月 2024, 於: Medical Image Analysis. 94, 103153.研究成果: Short survey › 同行評審
開啟存取32 引文 斯高帕斯（Scopus）