每年專案
個人檔案
研究專長
電子設計自動化、生物晶片設計自動化、微處理器設計、矽智財與系統單晶片設計
經歷
1998/07~2003/10 創意電子公司經理
2003/11~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, 電子工程, National Chiao Tung University
外部位置
指紋
查看啟用 Juinn-Dar Huang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
- 1 類似的個人檔案
網路
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料，或
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
1/08/24 → 31/07/25
研究計畫: Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
1/08/23 → 31/07/24
研究計畫: Other Government Ministry Institute
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智慧終端系統晶片研發與新創事業計畫-子計畫三：智慧終端晶片設計與驗證方法論之開發(2/2)
1/05/21 → 31/07/22
研究計畫: Other Government Ministry Institute
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An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability
Hu, C. H., Tseng, I. H., Kuo, P. H. & Huang, J. D., 2022, Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022. Institute of Electrical and Electronics Engineers Inc., p. 246-249 4 p. (Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022).研究成果: Conference contribution › 同行評審
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Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm
Song, L. Y., Kuo, T. C., Wang, M. H., Liu, C. N. J. & Huang, J. D., 2022, ASP-DAC 2022 - 27th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 80-85 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 2022-January).研究成果: Conference contribution › 同行評審
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Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets
Chou, W. C., Huang, C. W. & Huang, J. D., 2022, 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).研究成果: Conference contribution › 同行評審
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Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy
Fan, K. Y., Chen, J. H., Liu, C. N. & Huang, J. D., 2022, 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).研究成果: Conference contribution › 同行評審
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An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing
Lin, W. C., Chang, Y. C. & Huang, J. D., 6 6月 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021. Institute of Electrical and Electronics Engineers Inc., 9458511. (2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021).研究成果: Conference contribution › 同行評審
2 引文 斯高帕斯（Scopus）