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查看斯高帕斯 (Scopus) 概要
孫 元成
院長
產學創新研究學院
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4907
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37
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按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
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h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
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h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1982 …
2025
每年研究成果
概覽
指紋
網路
研究成果
(181)
類似的個人檔案
(6)
指紋
查看啟用 Jack Yuan-Chen Sun 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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Keyphrases
Annealing
18%
Avalanche
18%
BiCMOS Technology
19%
Bipolar Technology
66%
Bipolar Transistor
69%
Boron
21%
Channel Length
34%
CMOS Devices
24%
CMOS Technology
89%
Current Gain
37%
Cut-off Frequency
29%
Device Characteristics
26%
Device Design
20%
Emitter Width
17%
Emitter Windows
18%
Emitter-coupled Logic
21%
Epitaxial
53%
Epitaxial Si
21%
Floating Body
18%
Fmax
19%
Foundry
29%
Foundry Technology
18%
Gate Delay
35%
Gate Dielectric
17%
Gate Oxide
21%
Heterojunction Bipolar Transistors
25%
High Performance
80%
Inductors
17%
Intrinsic Basis
17%
Ion Implantation
20%
Liquid Nitrogen Temperature
29%
Low Operating Temperature
18%
Low Temperature
18%
MOSFET
30%
Nitrided Oxide
17%
Oxides
21%
Polysilicon
49%
Polysilicon Emitter
48%
Polysilicon Gate
18%
Profile Design
26%
RF CMOS
17%
Ring Oscillator
22%
Room Temperature
19%
Self-aligned
81%
Sheet Resistance
24%
Short Channel Effects
23%
SiGe
90%
System-on-chip
20%
TiSi2
18%
Transistor
95%
Engineering
Arsenic
30%
Atomic Hydrogen
17%
Bipolar Transistor
87%
Breakdown Voltage
18%
Channel Length
41%
Circuit Design
15%
Current Drain
13%
Current Drive
14%
Current Gain
49%
Current-Voltage Characteristic
16%
Cutoff Frequency
45%
Dangling Bond
12%
Device Performance
15%
Device Structure
13%
Dopants
18%
Electron Injection
16%
Emitter Coupled Logic Circuits
61%
Engineering
13%
Experimental Result
19%
Fits and Tolerances
12%
Floating Body
22%
Free Field
19%
Gate Dielectric
15%
Gate Length
18%
Gate Oxide
46%
Heterojunctions
34%
Interconnects
26%
Interface State
14%
Lithography
14%
Low-Temperature
48%
Metal-Oxide-Semiconductor Field-Effect Transistor
54%
Nitride
14%
Operation Temperature
18%
Optical Lithography
13%
Oscillator
23%
Oxide Thickness
24%
Passivation
16%
Polysilicon
100%
Power Supply
20%
Process Development
17%
Q Factor
23%
Rapid Thermal Annealing
16%
Room Temperature
25%
Series Resistance
22%
Sheet Resistance
26%
Silicon Dioxide
22%
Silicon on Insulator
32%
Supply Voltage
17%
System-on-Chip
36%
Transients
15%
