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查看斯高帕斯 (Scopus) 概要
張 錫嘉
教授
電子研究所
h-index
h10-index
h5-index
1647
引文
24
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
335
引文
9
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
54
引文
4
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1998 …
2024
每年研究成果
概覽
指紋
網路
計畫
(31)
研究成果
(179)
獎項
(11)
類似的個人檔案
(6)
指紋
查看啟用 Hsie-Chia Chang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
90-nm CMOS Technology
35%
Area-efficient
42%
BCH Decoder
16%
Berlekamp-Massey Algorithm
11%
Block Size
13%
Clock Frequency
11%
CMOS Process
21%
Code Rate
24%
Codec
15%
Codeword
20%
Countermeasure Circuit
11%
Cryptographic Processor
24%
Decoder
100%
Differential Power Analysis
10%
Dual-field
15%
Efficient Architecture
10%
Elliptic Curve Cryptography
22%
Encoder-decoder Architecture
21%
Energy Efficiency
19%
Error Correction Capability
11%
Flash Application
14%
Gate Count
26%
Gbps
13%
Hardware Complexity
13%
Hardware Cost
12%
Hardware Efficiency
13%
High Code Rate
14%
IEEE 802.15.3c
10%
Interleaver
14%
LDPC Codes
18%
LDPC Decoder
35%
Low Power
18%
Low-density Parity-check Codes
28%
Low-density Parity-check Convolutional Codes (LDPC-CCs)
22%
LT Codes
15%
NAND Flash
16%
NAND Flash Memory
11%
Non-binary LDPC Codes
12%
Parallel Architecture
16%
Power Consumption
24%
Radix-4
16%
Reconfigurable
22%
Reed-Solomon
20%
Reed-Solomon Decoder
28%
Ripple Height
10%
RS Encoder
14%
Trellis
16%
Turbo Decoder
36%
Variable Node
11%
Viterbi Decoder
18%
Engineering
Blocklength
11%
Capacitive
8%
Check Node
11%
Clock Frequency
9%
Code Rate
30%
Coding Gain
11%
Convergence Speed
9%
Convolutional Code
14%
Critical Path
13%
Cyclic Code
9%
Data Rate
24%
Decoder Implementation
17%
Decoding Algorithm
18%
Decoding Performance
15%
Electric Power Utilization
34%
Energy Conservation
23%
Energy Dissipation
12%
Energy Efficiency
23%
Energy Engineering
9%
Error Compensation
8%
Evaluator
9%
Experimental Result
12%
Flash Memory
22%
Floors
8%
Forward Error-Correction
9%
Frequency Operation
8%
Hardware Complexity
24%
Hardware Cost
13%
Input Symbol
9%
Interleaver
19%
Massey Berlekamp Algorithm
12%
Memory Access
11%
Multiple Code
11%
Network Routing
8%
Nodes
15%
Parallelism
8%
Parity Check Code
29%
Parity Check Matrix
9%
Performance Degradation
8%
Performance Loss
12%
Product Code
9%
Readout Circuit
8%
Reduce Power Consumption
8%
Side Channel Attack
9%
Simulation Result
26%
Supply Voltage
8%
System-on-Chip
9%
Test Result
10%
Transmissions
10%
Wireless Communication
8%
Computer Science
Approximation (Algorithm)
5%
Average Power Consumption
5%
Clock Frequency
10%
Code Construction
8%
Convolutional Code
25%
Critical Path
5%
Datapath
10%
Decoding Algorithm
11%
Decoding Performance
11%
Decoding Throughput
8%
Decryption
8%
Divider
6%
Elliptic Curve
21%
Elliptic curve scalar multiplication
5%
Energy Efficiency
26%
Energy Efficient
9%
Experimental Result
11%
Flash Memory
22%
Forward Error Correction
8%
Gradient Descent
5%
Hardware Architecture
5%
Hardware Cost
14%
Hardware Implementation
7%
High Throughput
15%
Input Symbol
7%
low density parity check code
12%
low-density parity-check code
16%
Machine Learning
9%
Memory Access
7%
Memory System
9%
Message Passing
7%
min-sum algorithm
26%
Minimal Polynomial
9%
Multiplexer
6%
Network Routing
11%
Neural Network
6%
Optical Communication
6%
Parallel Architectures
22%
Parallelism
8%
Parity Check Matrix
15%
Performance Degradation
5%
Performance Loss
5%
Power Analysis
26%
Power Consumption
21%
Power Dissipation
5%
radix-4
6%
Ring Oscillator
8%
Shifters
7%
Very large-scale integration (VLSI) architecture
6%
