Chien-Nan Jimmy Liu

查看斯高帕斯 (Scopus) 概要

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每年研究成果

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66 Conference contribution
42 Article
7 Conference article
2 Paper
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- 1 Chapter

7結果

篩選

2020
Achieving Analog Layout Integrity through Learning and Migration Invited Talk
Lin, M. P. H., Chi, H. Y., Patyal, A., Liu, Z. Y., Zhao, J. J., Liu, C-N. & Chen, H-M., 2 11月 2020, 於: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2020-November, 9256451.
研究成果: Conference article › 同行評審

開啟存取
3 引文斯高帕斯（Scopus）
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications
Chen, H-M., Hu, C. L., Chang, K. Y., Kuster, A., Lin, Y. H., Kuo, P. S., Chao, W. T., Lai, B. C., Liu, C-N. & Jou, S. J., 2 11月 2020, 於: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2020-November, 9256514.
研究成果: Conference article › 同行評審

開啟存取
4 引文斯高帕斯（Scopus）
2008
A scalable digitalized buffer for gigabit I/O
Lu, H., Su, C-C. & Liu, C-N., 26 12月 2008, 於: Proceedings of the Custom Integrated Circuits Conference. p. 241-244 4 p., 4672068.
研究成果: Conference article › 同行評審
1 引文斯高帕斯（Scopus）
2005
A novel approach for high-level power modeling of sequential circuits using recurrent neural networks
Hsieh, W. T., Shiue, C. C. & Liu, C-N., 1 12月 2005, 於: Proceedings - IEEE International Symposium on Circuits and Systems. p. 3591-3594 4 p., 1465406.
研究成果: Conference article › 同行評審
8 引文斯高帕斯（Scopus）
Estimating likelihood of correctness for error candidates to assist debugging faulty hdl designs
Jiang, T. Y., Jou, J. Y. & Liu, C-N., 1 12月 2005, 於: Proceedings - IEEE International Symposium on Circuits and Systems. p. 5682-5685 4 p., 1465927.
研究成果: Conference article › 同行評審
12 引文斯高帕斯（Scopus）
2004
A snapshot method to provide full visibility for functional debugging using FPGA
Chuang, C. L., Lu, D. J. & Liu, C-N., 1 12月 2004, 於: Proceedings of the Asian Test Symposium. p. 164-169 6 p.
研究成果: Conference article › 同行評審
7 引文斯高帕斯（Scopus）
2000
Novel approach for functional coverage measurement in HDL
Liu, C-N., Chang, C. Y., Jou, J. Y., Lai, M. C. & Juan, H. M., 1 1月 2000, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 4
研究成果: Conference article › 同行評審
13 引文斯高帕斯（Scopus）

劉 建男

研究成果

搜尋結果

Achieving Analog Layout Integrity through Learning and Migration Invited Talk

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications

A scalable digitalized buffer for gigabit I/O

A novel approach for high-level power modeling of sequential circuits using recurrent neural networks

Estimating likelihood of correctness for error candidates to assist debugging faulty hdl designs

A snapshot method to provide full visibility for functional debugging using FPGA

Novel approach for functional coverage measurement in HDL

劉建男