Chenming Hu

查看斯高帕斯 (Scopus) 概要

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每年研究成果

563 Article
265 Conference contribution
178 Conference article
88 Paper
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6結果

篩選

2003
Direct tunneling RAM (DT-RAM) for high-density memory applications
Kuo, C., King, T. J. & Hu, C.-M., 7月 2003, 於: Ieee Electron Device Letters. 24, 7, p. 475-477 3 p.
研究成果: Letter › 同行評審
3 引文斯高帕斯（Scopus）
RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology
Lam, S., Wan, H., Su, P., Wyatt, P. W., Chen, C. L., Niknejad, A. M., Hu, C.-M., Ko, P. K. & Chan, M., 1 4月 2003, 於: Ieee Electron Device Letters. 24, 4, p. 251-253 3 p.
研究成果: Letter › 同行評審
10 引文斯高帕斯（Scopus）
2002
A capacitorless double-gate DRAM cell
Kuo, C., King, T. J. & Hu, C.-M., 1 6月 2002, 於: IEEE Electron Device Letters. 23, 6, p. 345-347 3 p.
研究成果: Letter › 同行評審
81 引文斯高帕斯（Scopus）
Effects of high-κ gate dielectric materials on metal and silicon gate workfunctions
Yeo, Y. C., Ranade, P., King, T. J. & Hu, C.-M., 6月 2002, 於: Ieee Electron Device Letters. 23, 6, p. 342-344 3 p.
研究成果: Letter › 同行評審
197 引文斯高帕斯（Scopus）
Enhanced substrate current in SOI MOSFETs
Su, P., Goto, K. I., Sugii, T. & Hu, C.-M., 5月 2002, 於: Ieee Electron Device Letters. 23, 5, p. 282-284 3 p.
研究成果: Letter › 同行評審
18 引文斯高帕斯（Scopus）
1995
ESD Reliability and Protection Schemes in SOI CMOS Output Buffers
Chan, M., Yuen, S. S., Ma, Z. J., Hui, K. Y., Ko, P. K. & Hu, C.-M., 10月 1995, 於: IEEE Transactions on Electron Devices. 42, 10, p. 1816-1821 6 p.
研究成果: Letter › 同行評審

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9 引文斯高帕斯（Scopus）

胡 正明

研究成果

搜尋結果

Direct tunneling RAM (DT-RAM) for high-density memory applications

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

A capacitorless double-gate DRAM cell

Effects of high-κ gate dielectric materials on metal and silicon gate workfunctions

Enhanced substrate current in SOI MOSFETs

ESD Reliability and Protection Schemes in SOI CMOS Output Buffers

胡正明