!!Projects per year
個人檔案
研究專長
應用物理科學、工程科學
教育/學術資格
PhD, 電機及計算機, University of California, Berkeley
外部位置
指紋
查看啟用 Chenming Hu 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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過去五年中的合作和熱門研究領域
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專案
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Demonstration of Near Ideal Short Channel Effect in Lg = 25-nm Gate-All-Around Transistors Using Negative Capacitance Gate Stack
Park, J. H., Shanker, N., Hsu, S. L., Siker, U., Hu, C. & Salahuddin, S., 2026, 於: IEEE Electron Device Letters. 47, 3, p. 434-437 4 p.研究成果: Article › 同行評審
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Enhancement-Mode Monolayer WSe2 pFETs with Record Ion/Ioff at Contact Length of 30 nm
Su, Y. C., Wei, T. H., Lei, C., Shi, S., Hsu, Y. W., Su, T. C., Lee, S. Y., Lin, H. D., Chen, S. H., Chiang, H. L., Lin, C. C., Liu, B. H., Su, C. Y., Ke, C. C., Chang, S.-J., Wu, C. I., Hu, C., Fu, J. H., Tung, V. & Lee, T. E., 2026, 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).研究成果 › 同行評審
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First Demonstration of Heterogeneous n-IGZO/p-WSe2 Integration as a Power-Performance Area Booster for BEOL Complementary Gain-Cell Memory
Lin, H. D., Su, Y. C., Su, T. C., Ambrosi, E., Wu, C. H., Kuo, C. C., Chang, C. Y., Chiang, H. L., Wei, T. H., Hsu, Y. W., Huang, C. S., Lee, S. Y., Chang, W. N., Fu, J. H., Tung, V., Sun, J. Y. C., Hu, C., Wu, C. I., Lin, C. C. & Hou, T. H. 及其他2, , 2026, 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).研究成果 › 同行評審
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Interfacial-Layer-Free NCFETs Achieving 2 mV Hysteresis, 27mV/dec SS, 2mV/V DIBL, and Record 2088μA/μ m Ion at VDS=Vov=0.5 V
Lin, M. K., Liang, J. Y., Liu, Y. Q., Chen, W. J., Hsu, J. Y., Wu, X. H., Dai, J. N., Chen, Y. J., Yu, B. H., Fan, Z. E., Mei, Y. M., Lee, M. H., Chu, M. W., Su, P., Hu, C. & Liu, C. W., 2026, 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).研究成果 › 同行評審
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Investigating contact-limited scaling in sub-15-nm TMD FETs from first-principles
Lin, K. B., Liu, H. T., Wang, S. Y., Chang, S. J., Kaun, C. C. & Hu, C., 12月 2026, 於: npj Computational Materials. 12, 1, 79.研究成果: Article › 同行評審
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