Chao-Hsin Chien

2022

Aggressive Equivalent Oxide Thickness of 0.7 nm on Si_0.8Ge_0.2Through HfO₂ Dielectric Direct Deposition

Lee, M. C., Zhao, Y. Y., Chen, W. L., Wang, S. Y., Chen, Y. X., Luo, G. L. & Chien, C. H., 1 10月 2022, 於: Ieee Electron Device Letters. 43, 10, p. 1605-1608 4 p.

研究成果: Article › 同行評審

Electrical Characteristics of Si_0.8Ge_0.2p-MOSFET With TMA Pre-Doping and NH₃Plasma IL Treatment

Lee, M. C., Chung, N. J., Lin, H. R., Lee, W. L., Chung, Y. Y., Wang, S. Y., Luo, G. L. & Chien, C. H., 1 4月 2022, 於: IEEE Transactions on Electron Devices. 69, 4, p. 1776-1780 5 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

GaN-based mini-LED matrix applied to multi-functional forward lighting

Nguyen, Q. K., Lin, Y. J., Sun, C., Lee, X. H., Lin, S. K., Wu, C. S., Yang, T. H., Wu, T. L., Lee, T. X., Chien, C. H., Yu, Y. W. & Sun, C. C., 12月 2022, 於: Scientific reports. 12, 1, 6444.

研究成果: Article › 同行評審

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Impact of High-Temperature Annealing on Interfacial Layers Grown by O₂ Plasma on Si0.₅Ge_0.5 Substrates

Lee, M. C., Lin, H. R., Lee, W. L., Chung, N. J., Luo, G. L. & Chien, C. H., 1 3月 2022, 於: IEEE Transactions on Electron Devices. 69, 3, p. 1265-1270 6 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Van der Waals epitaxy of 2D h -AlN on TMDs by atomic layer deposition at 250 °c

Chang, S. J., Wang, S. Y., Huang, Y. C., Chih, J. H., Lai, Y. T., Tsai, Y. W., Lin, J. M., Chien, C. H., Tang, Y. T. & Hu, C., 18 4月 2022, 於: Applied Physics Letters. 120, 16, 162102.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

2021

High-Interface-Quality Hf-Based Gate Stacks on Si_0.5Ge_0.5Through Aluminum Capping

Lee, M. C., Lee, W. L., Lin, H. R., Luo, G. L. & Chien, C. H., 1 12月 2021, 於: Ieee Electron Device Letters. 42, 12, p. 1723-1726 4 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Improving thermal stability for ge p-mosfet of HfO₂-based gate stack with ti-doped into interfacial layer by in-situ plasma-enhanced atomic layer deposition

Li, H. H., Tsai, Y. H., Lin, Y. H. & Chien, C-H., 8月 2021, 於: Ieee Electron Device Letters. 42, 8, p. 1109-1111 3 p., 9448269.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Influence of Ti doping on the band gap and thermal stability of ultrathin GeO_xfilms

Yang, Y. C., Tsai, Y. H., Amrit, P., Chen, T. Y., Liu, H. T., Tang, S. J., Lin, C-L. & Chien, C-H., 8月 2021, 於: Journal of Physics D: Applied Physics. 54, 34, p. 1-7 7 p., 345102.

研究成果: Article › 同行評審

Time-dependent dielectric breakdown of gate oxide on 4H-SiC with different oxidation processes

Tsui, B-Y., Huang, Y. T., Wu, T-L. & Chien, C-H., 8月 2021, 於: Microelectronics Reliability. 123, 6 p., 114186.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

2020

High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory

Chung, Y. Y., Cheng, C. C., Chou, Y. C., Chueh, W. C., Chung, W. H., Yu, Z., Hung, T. Y. T., Huang, L. Y., Wang, S. Y., Teng, L. C., Chang, W. H., Li, L. J. & Chien, C-H., 11月 2020, 於: Ieee Electron Device Letters. 41, 11, p. 1649-1652 4 p., 9206053.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Impact of the Crystal Phase of ZrO₂ on Charge Trapping Memtransistor as Synaptic Device for Neural Network Application

Chou, Y. C., Tsai, C. W., Yi, C. Y., Chung, W. H. & Chien, C-H., 2020, 於: IEEE Journal of the Electron Devices Society. 8, p. 572-576 5 p., 9091548.

研究成果: Article › 同行評審

開啟存取

1 引文斯高帕斯（Scopus）

Improving the Performance of Charge Trapping MemTransistor as Synaptic Device by Ti-doped HfO2

Chou, Y. C., Chung, W. H., Tsai, C. W., Yi, C. Y. & Chien, C-H., 16 12月 2020, 於: IEEE Journal of the Electron Devices Society. 9, p. 137-143 7 p., 9296335.

研究成果: Article › 同行評審

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Neuro-Inspired-in-Memory Computing Using Charge-Trapping MemTransistor on Germanium as Synaptic Device

Chou, Y. C., Tsai, C. W., Yi, C. Y., Chung, W. H., Wang, S. Y. & Chien, C-H., 9月 2020, 於: IEEE Transactions on Electron Devices. 67, 9, p. 3605-3609 5 p., 9153812.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Study of E-Mode AlGaN/GaN MIS-HEMT with La-silicate Gate Insulator for Power Applications

Huang, K. N., Lin, Y. C., Lin, J. C., Hsu, C. C., Lee, J. H., Wu, C. H., Yao, J. N., Hsu, H-T., Nagarajan, V., Kakushima, K., Tsutsui, K., Iwai, H., Chien, C-H. & Chang, E. Y., 2月 2020, 於: Journal of Electronic Materials. 49, 2, p. 1348-1353 6 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Study of tri-gate AlGaN/GaN MOS-HEMTs for power application

Huang, K. N., Lin, Y. C., Lee, J. H., Hsu, C. C., Yao, J. N., Wu, C. Y., Chien, C. H. & Chang, E. Y., 11月 2020, 於: Micro and Nano Engineering. 9, 100073.

研究成果: Article › 同行評審

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4 引文斯高帕斯（Scopus）

2019

Comparison of the Physical and Electrical Properties of HfO2/Al2O3/HfO2/GeO x /Ge and HfO2/Al2O3/GeO x /Ge Gate Stacks

Tsai, Y. H., Chou, C. H., Li, H. H., Yeh, W-K., Lin, Y. H., Ko, F-H. & Chien, C-H., 8月 2019, 於: Journal of Nanoscience and Nanotechnology. 19, 8, p. 4529-4534 6 p.

研究成果: Article › 同行評審

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS₂ Channel Directly Grown on SiO_x/Si Substrates Using Area-Selective CVD Technology

Chung, Y. Y., Shieh, J. M., Su, S. K., Chiang, H. L., Chen, T. C., Li, L. J., Wong, H. S. P., Jian, W-B., Chien, C-H., Lu, K. C., Cheng, C. C., Li, M. Y., Lin, C. T., Li, C. F., Chen, J. H., Lai, T. Y. & Li, K. S., 12月 2019, 於: IEEE Transactions on Electron Devices. 66, 12, p. 5381-5386 6 p., 8889483.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

Demonstration of HfO ₂ -Based Gate Dielectric with Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti into Interfacial Layer

Tsai, Y. H., Chou, C. H., Chung, Y. Y., Yeh, W. K., Lin, Y. H., Ko, F-H. & Chien, C-H., 1 2月 2019, 於: IEEE Electron Device Letters. 40, 2, p. 174-176 3 p., 8579236.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Experimentally Determining the Top and Edge Contact Resistivities of Two-step Sulfurization Nb-Doped MoS2 Films Using the Transmission Line Measurement

Chung, Y. Y., Li, C. F., Lin, C. T., Ho, Y. T. & Chien, C. H., 1 1月 2019, (Accepted/In press) 於: IEEE Electron Device Letters.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Improving Interface State Density and Thermal Stability of High-κ Gate Stack Through High-Vacuum Annealing on Si_0.5Ge_0.5

Lee, W. L., Yu, C. Y., Zhang, J. L., Luo, G. L. & Chien, C-H., 1 5月 2019, 於: IEEE Electron Device Letters. 40, 5, p. 678-681 4 p., 8667385.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

2018

Enhancing the thermal stability of GaSb Schottky-Barrier MOSFET with Pt Source/Drain

Tsai, M. L., Chang, Y. P. & Chien, C-H., 1 7月 2018, 於: IEEE Electron Device Letters. 39, 7, p. 939-942 4 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

First Experimental Demonstration and Mechanism of Abnormal Palladium Diffusion Induced by Excess Interstitial Ge

Chou, C. H., Shih, A. S., Yu, S. C., Lin, Y. H., Tsai, Y. H., Lin, C-Y., Yeh, W. K. & Chien, C-H., 1 11月 2018, 於: IEEE Electron Device Letters. 39, 11, p. 1632-1635 4 p., 8470143.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Incorporating yttrium into a GeO interfacial layer with HfO₂-based gate stack on Ge

Chou, C-H., Lu, Y. H., Tsai, Y. H., Shih, A. S., Yeh, W. K. & Chien, C. H., 19 1月 2018, 於: ECS Journal of Solid State Science and Technology. 7, 2, p. N15-N19 5 p.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

Integration of microwave-annealed oxidation on germanium metal-oxide-semiconductor devices

Hsu, C. C., Chi, W. C., Tsai, Y. H., Tsai, M. L., Wang, S. Y., Chou, C. H., Zhang, J. L., Luo, G. L. & Chien, C-H., 1 9月 2018, 於: Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics. 36, 5, 051204.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Phase-separation phenomenon of NiGePt alloy on n-Ge by microwave annealing

Hsu, C. C., Lin, K. L., Chi, W. C., Chou, C. H., Luo, G. L., Lee, Y. J. & Chien, C-H., 30 4月 2018, 於: Journal of Alloys and Compounds. 743, p. 262-267 6 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Study of high-ge-content Si0.16Ge0.84 gate stack by low pressure oxidation

Lee, W. L., Zhang, J. L., Tsai, M. L., Wang, S. Y., Luo, G. L. & Chien, C. H., 1月 2018, 於: ECS Journal of Solid State Science and Technology. 7, 2, p. P73-P76

研究成果: Article › 同行評審

Study of the band alignment between atomic-layer-deposited high-κ dielectrics and MoS₂ film

Chung, Y. Y., Tsai, M. L., Ho, Y. T., Tseng, Y. C. & Chien, C. H., 1月 2018, 於: ECS Journal of Solid State Science and Technology. 7, 4, p. N46-N50

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

2017

Experimental Realization of Thermal Stability Enhancement of Nickel Germanide Alloy by Using TiN Metal Capping

Chou, C-H., Tsai, Y. H., Hsu, C. C., Jau, Y. H., Lin, Y. H., Yeh, W. K. & Chien, C-H., 1 5月 2017, 於: IEEE Transactions on Electron Devices. 64, 5, p. 2314-2320 7 p., 7885604.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

Fully depleted GeOI-channel junctionless pMOSFET with a low-resistance-raised NiGe alloy S/D

Lee, W. L., Hsu, C. C., Chung, C. T., Lu, Y. H., Luo, G. L. & Chien, C-H., 1 1月 2017, 於: ECS Journal of Solid State Science and Technology. 6, 8, p. P507-P511

研究成果: Article › 同行評審

Highly scaled equivalent oxide thickness of 0.66nm for TiN/HfO₂/GaSb MOS capacitors by using plasma-enhanced atomic layer deposition

Tsai, M. L., Wang, S. Y. & Chien, C-H., 1 8月 2017, 於: Applied Physics Express. 10, 8, 086501.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

2016

Experimental Realization of a Ternary-Phase Alloy Through Microwave-Activated Annealing for Ge Schottky pMOSFETs

Hsu, C. C., Chi, W. C., Tsai, Y. H., Chou, C. H., Chen, C. W., Chien, H. P., Chuang, S. S., Luo, G. L., Lee, Y. J. & Chien, C. H., 1 7月 2016, 於: IEEE Transactions on Electron Devices. 63, 7, p. 2714-2721 8 p., 7484321.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

High-Performance Schottky Contact Quantum-Well Germanium Channel pMOSFET with Low Thermal Budget Process

Hsu, C. C., Tsai, Y. H., Chen, C. W., Li, J. H., Lin, Y. H., Lee, Y. J., Luo, G. L. & Chien, C-H., 1 1月 2016, 於: IEEE Electron Device Letters. 37, 1, p. 8-11 4 p., 7331593.

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

Improving Thermal Stability and Interface State Density of High-κ Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium

Tsai, Y. H., Chou, C. H., Shih, A. S., Jau, Y. H., Yeh, W. K., Lin, Y. H., Ko, F-H. & Chien, C-H., 1 11月 2016, 於: IEEE Electron Device Letters. 37, 11, p. 1379-1382 4 p., 7577750.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

Interface Characterization of HfO₂/GaSb MOS Capacitors with Ultrathin Equivalent Oxide Thickness by Using Hydrogen Plasma Treatment

Tsai, M. L., Ko, J. Y., Wang, S. Y. & Chien, C-H., 1 9月 2016, 於: IEEE Transactions on Electron Devices. 63, 9, p. 3459-3465 7 p., 7515183.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

Low-leakage tetragonal ZrO ₂ (EOT < 1 nm) with in situ plasma interfacial passivation on germanium

Chou, C-H., Chang, H. H., Hsu, C. C., Yeh, W. K. & Chien, C-H., 1 2月 2016, 於: IEEE Electron Device Letters. 37, 2, p. 138-141 4 p., 7358074.

研究成果: Article › 同行評審

13 引文斯高帕斯（Scopus）

2015

Applying dielectrophoresis on silver nanowires alignment and assembly to enhance the efficiency of plasmonic silicon solar cells

Lin, C. C., Wang, S. Y., Lin, W. L., Lin, Y. L., Cheng, C., Sun, W. H., Chen, Z. L., Chien, C-H. & Ko, F-H., 7月 2015, 於: International Journal of Electrochemical Science. 10, 9, p. 7192-7199 8 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Effect of passivation layer on InGaZnO thin-film transistors with hybrid silver nanowires as source and drain electrodes

Yu, C. H., Wu, H. C. & Chien, C-H., 1 8月 2015, 於: Japanese journal of applied physics. 54, 8, 081101.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Fabricating a n⁺-Ge contact with ultralow specific contact resistivity by introducing a PtGe alloy as a contact metal

Hsu, C. C., Chou, C. H., Wang, S. Y., Chi, W. C., Chien, C. H. & Luo, G. L., 14 9月 2015, 於: Applied Physics Letters. 107, 11, 113503.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

Microwave annealing for NiSiGe Schottky junction on SiGe P-channel

Lin, Y. H., Tsai, Y. H., Hsu, C. C., Luo, G. L., Lee, Y. J. & Chien, C-H., 1 1月 2015, 於: Materials. 8, 11, p. 7519-7523 5 p.

研究成果: Article › 同行評審

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1 引文斯高帕斯（Scopus）

Ultrathin single-crystalline silicon solar cells for mechanically flexible and optimal surface morphology designs

Lin, C. C., Chuang, Y. J., Sun, W. H., Cheng, C., Chen, Y. T., Chen, Z. L., Chien, C-H. & Ko, F-H., 1 9月 2015, 於: Microelectronic Engineering. 145, p. 128-132 5 p.

研究成果: Article › 同行評審

21 引文斯高帕斯（Scopus）

2014

Body-tied germanium tri-gate junctionless PMOSFET with in-situ boron doped channel

Chen, C. W., Chung, C. T., Tzeng, J. Y., Chang, P. S., Luo, G. L. & Chien, C-H., 1 1月 2014, 於: IEEE Electron Device Letters. 35, 1, p. 12-14 3 p., 6684319.

研究成果: Article › 同行評審

14 引文斯高帕斯（Scopus）

Effect of Mg doping on the electrical characteristics of high performance IGZO Thin Film Transistors

Wu, H. C., Liu, T. S. & Chien, C-H., 17 2月 2014, 於: ECS Journal of Solid State Science and Technology. 3, 2

研究成果: Article › 同行評審

14 引文斯高帕斯（Scopus）

Enhancing the performance of germanium channel nMOSFET using phosphorus dopant segregation

Chen, C. W., Tzeng, J. Y., Chung, C. T., Chien, H. P., Chien, C-H., Luo, G. L., Wang, P. Y. & Tsui, B-Y., 1 1月 2014, 於: IEEE Electron Device Letters. 35, 1, p. 6-8 3 p., 6679233.

研究成果: Article › 同行評審

14 引文斯高帕斯（Scopus）

Experimental demonstration of (111)-oriented GaAs metal-oxide-semiconductor field-effect-transistors with hetero-epitaxial Ge source/drain

Han, T. Y., Luo, G. L., Cheng, C. C., Ko, C. H., Wann, C. H., Kei, C. C., Hsiao, C. N. & Chien, C-H., 1 1月 2014, 於: ECS Journal of Solid State Science and Technology. 3, 4, p. P86-P90

研究成果: Article › 同行評審

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Highly transparent, high-performance IGZO-TFTs using the selective formation of IGZO source and drain electrodes

Wu, H. C. & Chien, C-H., 1 1月 2014, 於: IEEE Electron Device Letters. 35, 6, p. 645-647 3 p., 6809183.

研究成果: Article › 同行評審

17 引文斯高帕斯（Scopus）

High-performance germanium p-and n-MOSFETs with NiGe Source/Drain

Chen, C. W., Tzeng, J. Y., Chung, C. T., Chien, H. P., Chien, C-H. & Luo, G. L., 1 1月 2014, 於: IEEE Transactions on Electron Devices. 61, 8, p. 2656-2661 6 p., 6844018.

研究成果: Article › 同行評審

15 引文斯高帕斯（Scopus）

2013

Epitaxial germanium on soi substrate and its application of fabricating high i on I_OFF ratio Ge FinFETs

Chung, C. T., Chen, C. W., Lin, J. C., Wu, C. C., Chien, C-H., Luo, G. L., Kei, C. C. & Hsiao, C. N., 29 5月 2013, 於: IEEE Transactions on Electron Devices. 60, 6, p. 1878-1883 6 p., 6515139.

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

Germanium N and P multifin field-effect transistors with high-performance germanium (Ge)p⁺n and n⁺p heterojunctions formed on si substrate

Chen, C. W., Chung, C. T., Tzeng, J. Y., Li, P. H., Chang, P. S., Chien, C-H. & Luo, G. L., 3 4月 2013, 於: IEEE Transactions on Electron Devices. 60, 4, p. 1334-1341 8 p., 6482668.

研究成果: Article › 同行評審

12 引文斯高帕斯（Scopus）

HfO₂ nanocrystal memory on SiGe channel

Lin, Y. H. & Chien, C-H., 1 1月 2013, 於: Solid-State Electronics. 80, p. 5-9 5 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

High On/Off ratio and very low leakage in p⁺/n and n ⁺/p germanium/silicon heterojunction diodes

Chen, C. W., Chung, C. T., Lin, J. C., Luo, G. L. & Chien, C-H., 1 2月 2013, 於: Applied Physics Express. 6, 2, 024001.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

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