每年專案
個人檔案
研究專長
元件物理、奈米元件技術、奈米記憶體元件技術、ULSI製程、元件可靠性分析
經歷
1999/09~2005/08 國研院國家奈米元件實驗室副研究員
2005/08~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, 電機工程, National Chiao Tung University
外部位置
指紋
查看啟用 Chao-Hsin Chien 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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網路
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料，或
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以原子層沉積技術來製作高品質金屬摻雜於介面層之應用於垂直堆疊式高遷移率鍺通道奈米片電晶體之研究
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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以原子層沉積技術來製作高品質金屬摻雜於介面層之應用於垂直堆疊式高遷移率鍺通道奈米片電晶體之研究
1/08/21 → 31/07/22
研究計畫: Other Government Ministry Institute
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以原子層沉積技術來製作高品質金屬摻雜於介面層之應用於垂直堆疊式高遷移率鍺通道奈米片電晶體之研究
1/08/20 → 31/07/21
研究計畫: Other Government Ministry Institute
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Aggressive Equivalent Oxide Thickness of 0.7 nm on Si0.8Ge0.2Through HfO2 Dielectric Direct Deposition
Lee, M. C., Zhao, Y. Y., Chen, W. L., Wang, S. Y., Chen, Y. X., Luo, G. L. & Chien, C. H., 1 10月 2022, 於: Ieee Electron Device Letters. 43, 10, p. 1605-1608 4 p.研究成果: Article › 同行評審
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Comprehensive Physics Based TCAD Model for 2D MX2Channel Transistors
Sathaiya, D. M., Hung, T. Y. T., Chen, E., Wu, W. C., Wei, A., Chuu, C. P., Su, S. K., Chou, A. S., Chung, C. T., Chien, C. H., Wang, H., Cai, J., Wu, C. C., Radu, I. P. & Wu, J., 2022, 2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc., p. 2841-2844 4 p. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2022-December).研究成果: Conference contribution › 同行評審
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Demonstration of HfO2-Based Gate Stacks with Ultralow Interface State Density and Leakage Current on Ge pMOSFET by Adding Hafnium into GeOx Interfacial Layer
Li, H. H., Chen, S. C., Lin, Y. H. & Chien, C. H., 2022, Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022. Ye, F. & Tang, T-A. (編輯). Institute of Electrical and Electronics Engineers Inc., (Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022).研究成果: Conference contribution › 同行評審
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Electrical Characteristics of Si0.8Ge0.2p-MOSFET With TMA Pre-Doping and NH3Plasma IL Treatment
Lee, M. C., Chung, N. J., Lin, H. R., Lee, W. L., Chung, Y. Y., Wang, S. Y., Luo, G. L. & Chien, C. H., 1 4月 2022, 於: IEEE Transactions on Electron Devices. 69, 4, p. 1776-1780 5 p.研究成果: Article › 同行評審
1 引文 斯高帕斯（Scopus） -
First Demonstration of GAA Monolayer-MoS2Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length
Chung, Y. Y., Chou, B. J., Hsu, C. F., Yun, W. S., Li, M. Y., Su, S. K., Liao, Y. T., Lee, M. C., Huang, G. W., Liew, S. L., Shen, Y. Y., Chang, W. H., Chen, C. W., Kei, C. C., Wang, H., Philip Wong, H. S., Lee, T. Y., Chien, C. H., Cheng, C. C. & Radu, I. P., 2022, 2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc., p. 3451-3454 4 p. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2022-December).研究成果: Conference contribution › 同行評審