Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins

Ming-Dou Ker; Hun Hsien Chang

doi:10.1109/VTSA.1999.786059

Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins

Ming-Dou Ker^*, Hun Hsien Chang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in the CMOS IC which has multiple mixed-voltage power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and quickly discharged through the desired ESD protection devices. By using the ESD buses, the CMOS IC with separated power pins can be safety protected against the ESD damages which is often located in the internal circuits.

Original language	English
Pages (from-to)	298-301
Number of pages	4
Journal	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs	https://doi.org/10.1109/VTSA.1999.786059
State	Published - 1 Jan 1999
Event	Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan Duration: 7 Jun 1999 → 10 Jun 1999

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title = "Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins",

abstract = "A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in the CMOS IC which has multiple mixed-voltage power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and quickly discharged through the desired ESD protection devices. By using the ESD buses, the CMOS IC with separated power pins can be safety protected against the ESD damages which is often located in the internal circuits.",

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year = "1999",

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AU - Chang, Hun Hsien

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N2 - A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in the CMOS IC which has multiple mixed-voltage power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and quickly discharged through the desired ESD protection devices. By using the ESD buses, the CMOS IC with separated power pins can be safety protected against the ESD damages which is often located in the internal circuits.

AB - A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in the CMOS IC which has multiple mixed-voltage power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and quickly discharged through the desired ESD protection devices. By using the ESD buses, the CMOS IC with separated power pins can be safety protected against the ESD damages which is often located in the internal circuits.

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U2 - 10.1109/VTSA.1999.786059

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M3 - Conference article

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JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Y2 - 7 June 1999 through 10 June 1999

ER -

Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins

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