Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

Ming-Dou Ker; Chung-Yu Wu; Hun Hsien Chang; Tain Shun Wu

doi:10.1109/CICC.1997.606579

Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

Ming-Dou Ker^*, Chung-Yu Wu, Hun Hsien Chang, Tain Shun Wu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

13 Scopus citations

Abstract

A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an 8-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV.

Original language	English
Pages (from-to)	31-34
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1997.606579
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 5 May 1997 → 8 May 1997

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title = "Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology",

abstract = "A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an 8-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV.",

author = "Ming-Dou Ker and Chung-Yu Wu and Chang, {Hun Hsien} and Wu, {Tain Shun}",

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T1 - Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Chang, Hun Hsien

AU - Wu, Tain Shun

PY - 1997/1/1

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N2 - A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an 8-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV.

AB - A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC's against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an 8-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV.

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JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

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ER -

Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

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