An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification.
|Number of pages||5|
|State||Published - 1 Dec 1994|
|Event||Proceedings of the 1994 International Integrated Reliability Workshop Final Report - Lake Tahoe, CA, USA|
Duration: 16 Oct 1994 → 19 Oct 1994
|Conference||Proceedings of the 1994 International Integrated Reliability Workshop Final Report|
|City||Lake Tahoe, CA, USA|
|Period||16/10/94 → 19/10/94|