A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong|
Duration: 9 Jun 1997 → 12 Jun 1997