Whole-chip ESD protection design for submicron CMOS VLSI

Ming-Dou Ker; Shue Chang Liu

doi:10.1109/ISCAS.1997.621526

Whole-chip ESD protection design for submicron CMOS VLSI

Ming-Dou Ker^*, Shue Chang Liu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.

Original language	English
Pages (from-to)	1920-1923
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/ISCAS.1997.621526
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 9 Jun 1997 → 12 Jun 1997

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10.1109/ISCAS.1997.621526

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title = "Whole-chip ESD protection design for submicron CMOS VLSI",

abstract = "A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.",

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AU - Liu, Shue Chang

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N2 - A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.

AB - A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.

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U2 - 10.1109/ISCAS.1997.621526

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M3 - Conference article

AN - SCOPUS:0030655083

SN - 0271-4310

VL - 3

SP - 1920

EP - 1923

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

Y2 - 9 June 1997 through 12 June 1997

ER -

Whole-chip ESD protection design for submicron CMOS VLSI

Abstract

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