Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies

Ming Fang Lai, Shih Wei Li, Jian Yu Shih, Kuan-Neng Chen*

*Corresponding author for this work

    Research output: Contribution to journalReview articlepeer-review

    36 Scopus citations


    Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.

    Original languageEnglish
    Pages (from-to)3282-3286
    Number of pages5
    JournalMicroelectronic Engineering
    Issue number11
    StatePublished - 1 Nov 2011


    • Three-dimensional integrated circuits (3D IC)
    • Through-silicon via (TSV)
    • Wafer bonding


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