TY - JOUR
T1 - Wafer-level three-dimensional integrated circuits (3D IC)
T2 - Schemes and key technologies
AU - Lai, Ming Fang
AU - Li, Shih Wei
AU - Shih, Jian Yu
AU - Chen, Kuan-Neng
PY - 2011/11/1
Y1 - 2011/11/1
N2 - Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.
AB - Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.
KW - Three-dimensional integrated circuits (3D IC)
KW - Through-silicon via (TSV)
KW - Wafer bonding
UR - http://www.scopus.com/inward/record.url?scp=80053355092&partnerID=8YFLogxK
U2 - 10.1016/j.mee.2011.05.036
DO - 10.1016/j.mee.2011.05.036
M3 - Review article
AN - SCOPUS:80053355092
SN - 0167-9317
VL - 88
SP - 3282
EP - 3286
JO - Microelectronic Engineering
JF - Microelectronic Engineering
IS - 11
ER -