TY - JOUR
T1 - Wafer-level 3D integration technology
AU - Koester, Steven J.
AU - Young, Albert M.
AU - Yu, Roy R.
AU - Purushothaman, Sampath
AU - Chen, Kuan-Neng
AU - La Tulipe, Douglas C.
AU - Rana, Narender
AU - Shi, Leathen
AU - Wordeman, Matthew R.
AU - Sprogis, Edmund J.
PY - 2008
Y1 - 2008
N2 - An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.
AB - An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.
UR - https://www.scopus.com/pages/publications/61649096165
U2 - 10.1147/JRD.2008.5388565
DO - 10.1147/JRD.2008.5388565
M3 - Review article
AN - SCOPUS:61649096165
SN - 0018-8646
VL - 52
SP - 583
EP - 597
JO - IBM Journal of Research and Development
JF - IBM Journal of Research and Development
IS - 6
ER -