VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode

Shyh-Jye Jou; Chun Hung Kuo; Muh Tian Shiau; Jung Yu Heh; Chrong Kuang Wang

doi:10.1109/VTSA.1999.786024

VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode

Shyh-Jye Jou^*, Chun Hung Kuo, Muh Tian Shiau, Jung Yu Heh, Chrong Kuang Wang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV will be introduced. The proposed TR uses a simple and baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6um 1P3M process. The total gate is 12985 and the core size is 2175 by 1237 um ² . It consumes only 7.32 mW when operates at 2 V.

Original language	English
Pages (from-to)	159-162
Number of pages	4
Journal	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs	https://doi.org/10.1109/VTSA.1999.786024
State	Published - 1 Jan 1999
Event	Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan Duration: 7 Jun 1999 → 10 Jun 1999

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title = "VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode",

abstract = " In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV will be introduced. The proposed TR uses a simple and baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6um 1P3M process. The total gate is 12985 and the core size is 2175 by 1237 um 2 . It consumes only 7.32 mW when operates at 2 V. ",

author = "Shyh-Jye Jou and Kuo, {Chun Hung} and Shiau, {Muh Tian} and Heh, {Jung Yu} and Wang, {Chrong Kuang}",

year = "1999",

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doi = "10.1109/VTSA.1999.786024",

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journal = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

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note = "null ; Conference date: 07-06-1999 Through 10-06-1999",

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TY - JOUR

T1 - VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode

AU - Jou, Shyh-Jye

AU - Kuo, Chun Hung

AU - Shiau, Muh Tian

AU - Heh, Jung Yu

AU - Wang, Chrong Kuang

PY - 1999/1/1

Y1 - 1999/1/1

N2 - In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV will be introduced. The proposed TR uses a simple and baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6um 1P3M process. The total gate is 12985 and the core size is 2175 by 1237 um 2 . It consumes only 7.32 mW when operates at 2 V.

AB - In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV will be introduced. The proposed TR uses a simple and baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6um 1P3M process. The total gate is 12985 and the core size is 2175 by 1237 um 2 . It consumes only 7.32 mW when operates at 2 V.

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U2 - 10.1109/VTSA.1999.786024

DO - 10.1109/VTSA.1999.786024

M3 - Conference article

AN - SCOPUS:0032599207

SP - 159

EP - 162

JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SN - 1524-766X

Y2 - 7 June 1999 through 10 June 1999

ER -

VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode

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