TY - JOUR
T1 - VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode
AU - Jou, Shyh-Jye
AU - Kuo, Chun Hung
AU - Shiau, Muh Tian
AU - Heh, Jung Yu
AU - Wang, Chrong Kuang
PY - 1999/1/1
Y1 - 1999/1/1
N2 -
In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV will be introduced. The proposed TR uses a simple and baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6um 1P3M process. The total gate is 12985 and the core size is 2175 by 1237 um
2
. It consumes only 7.32 mW when operates at 2 V.
AB -
In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV will be introduced. The proposed TR uses a simple and baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6um 1P3M process. The total gate is 12985 and the core size is 2175 by 1237 um
2
. It consumes only 7.32 mW when operates at 2 V.
UR - http://www.scopus.com/inward/record.url?scp=0032599207&partnerID=8YFLogxK
U2 - 10.1109/VTSA.1999.786024
DO - 10.1109/VTSA.1999.786024
M3 - Conference article
AN - SCOPUS:0032599207
SN - 1524-766X
SP - 159
EP - 162
JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications
Y2 - 7 June 1999 through 10 June 1999
ER -