TY - GEN
T1 - VLSI implementation of a low complexity 4×4 MIMO sphere decoder with table enumeration
AU - Yang, Kai Jiun
AU - Tsai, Shang-Ho
AU - Chang, Ruei Ching
AU - Chen, Yan Cheng
AU - Chuang, Gene C.H.
PY - 2013
Y1 - 2013
N2 - In this work a sphere decoder with low complexity is proposed and implemented. We propose a simplified norm algorithm, which is called admissible set elimination (ASE), to dramatically decrease the number of searching nodes. In addition, the decoder uses table-look-up to acquire the enumeration order of different constellations. As a result, the critical path is shortened and the throughput is enhanced. Compared to the optimal ML detector, the proposed scheme greatly improves the complexity and throughput, while the performance only degrades around 0.5 dB. The proposed scheme is fabricated by a TSMC 90 nm process. The area is 0.85 mm2, and the average throughput can be up to 411.3 Mbps when the clock rate is 108.7 MHz.
AB - In this work a sphere decoder with low complexity is proposed and implemented. We propose a simplified norm algorithm, which is called admissible set elimination (ASE), to dramatically decrease the number of searching nodes. In addition, the decoder uses table-look-up to acquire the enumeration order of different constellations. As a result, the critical path is shortened and the throughput is enhanced. Compared to the optimal ML detector, the proposed scheme greatly improves the complexity and throughput, while the performance only degrades around 0.5 dB. The proposed scheme is fabricated by a TSMC 90 nm process. The area is 0.85 mm2, and the average throughput can be up to 411.3 Mbps when the clock rate is 108.7 MHz.
UR - http://www.scopus.com/inward/record.url?scp=84883414572&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2013.6572304
DO - 10.1109/ISCAS.2013.6572304
M3 - Conference contribution
AN - SCOPUS:84883414572
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2167
EP - 2170
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -