@inproceedings{e569970685804ebc944df8391b13c497,
title = "VLSI focal-plane array processor for morphological image processing",
abstract = "A full-custom mixed-signal VLSI design for high-speed morphological image processing is developed by combining a two-dimensional fine-grain parallel array architecture with on-chip focal-plane photodetectors and transmitters. An 8∗8 array processor prototype chip is designed in a 1.2-mm∗1.2-mm silicon area using the MOSIS 2- mu m CMOS process.",
author = "Fang, {W. C.} and T. Shaw and J. Yu",
year = "1992",
month = jan,
day = "1",
doi = "10.1109/ASIC.1992.270255",
language = "English",
series = "Proceedings of International Conference on ASIC",
publisher = "IEEE Computer Society",
pages = "423--426",
booktitle = "Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992",
address = "United States",
note = "5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 ; Conference date: 21-09-1992 Through 25-09-1992",
}