We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φm-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting, IEDM|
|State||Published - 1 Dec 2007|
|Event||2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States|
Duration: 10 Dec 2007 → 12 Dec 2007