Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chris Chun Chih Chung; Chiuan Huei Shen; Jer Yi Lin; Chun Chieh Chin; Tien-Sheng Chao

doi:10.1109/TED.2017.2780851

Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chris Chun Chih Chung, Chiuan Huei Shen, Jer Yi Lin, Chun Chieh Chin, Tien-Sheng Chao^*

^*Corresponding author for this work

Department of Electrophysics

Research output: Contribution to journal › Article › peer-review

18 Scopus citations

Abstract

We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.

Original language	English
Article number	8233410
Pages (from-to)	756-762
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	65
Issue number	2
DOIs	https://doi.org/10.1109/TED.2017.2780851
State	Published - Feb 2018

Keywords

Cantilever
high-k metal gate (HKMG)
junctionless
nanowire
series resistance
vertically stacked.

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title = "Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit",

abstract = "We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.",

keywords = "Cantilever, high-k metal gate (HKMG), junctionless, nanowire, series resistance, vertically stacked.",

author = "Chung, {Chris Chun Chih} and Shen, {Chiuan Huei} and Lin, {Jer Yi} and Chin, {Chun Chieh} and Tien-Sheng Chao",

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AU - Lin, Jer Yi

AU - Chin, Chun Chieh

AU - Chao, Tien-Sheng

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N2 - We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.

AB - We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.

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Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

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Keywords

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