Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin; Pin Hsin Chang; Rong Kun Chang; Ming-Dou Ker; Wen Tai Wang

doi:10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin, Pin Hsin Chang, Rong Kun Chang, Ming-Dou Ker, Wen Tai Wang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

Original language	English
Title of host publication	Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	255-258
Number of pages	4
ISBN (Electronic)	9781479999286, 9781479999286
DOIs	https://doi.org/10.1109/IPFA.2015.7224380
State	Published - 25 Aug 2015
Event	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan Duration: 29 Jun 2015 → 2 Jul 2015

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume	2015-August

Conference

Conference	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
Country/Territory	Taiwan
City	Hsinchu
Period	29/06/15 → 2/07/15

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10.1109/IPFA.2015.7224380

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Lin, C. Y., Chang, P. H., Chang, R. K., Ker, M-D., & Wang, W. T. (2015). Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. In Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 (pp. 255-258). [7224380] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2015.7224380

Lin, Chun Yu ; Chang, Pin Hsin ; Chang, Rong Kun et al. / Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 255-258 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{a36ded8ab9874ddcae10b5cfbf2dbbc8,

title = "Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology",

abstract = "A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.",

author = "Lin, {Chun Yu} and Chang, {Pin Hsin} and Chang, {Rong Kun} and Ming-Dou Ker and Wang, {Wen Tai}",

year = "2015",

month = aug,

day = "25",

doi = "10.1109/IPFA.2015.7224380",

language = "English",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "255--258",

booktitle = "Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015",

address = "United States",

note = "null ; Conference date: 29-06-2015 Through 02-07-2015",

}

Lin, CY, Chang, PH, Chang, RK, Ker, M-D & Wang, WT 2015, Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. in Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015., 7224380, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. 255-258, 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015, Hsinchu, Taiwan, 29/06/15. https://doi.org/10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. / Lin, Chun Yu; Chang, Pin Hsin; Chang, Rong Kun et al.

Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 255-258 7224380 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

AU - Lin, Chun Yu

AU - Chang, Pin Hsin

AU - Chang, Rong Kun

AU - Ker, Ming-Dou

AU - Wang, Wen Tai

PY - 2015/8/25

Y1 - 2015/8/25

N2 - A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

AB - A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

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U2 - 10.1109/IPFA.2015.7224380

DO - 10.1109/IPFA.2015.7224380

M3 - Conference contribution

AN - SCOPUS:84949811797

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

SP - 255

EP - 258

BT - Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 29 June 2015 through 2 July 2015

ER -

Lin CY, Chang PH, Chang RK, Ker M-D, Wang WT. Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. In Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 255-258. 7224380. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

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