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VecRA: A vector-aware register allocator for GPU shader processors
Yi-Ping You
, Szu Chien Chen
Institute of Computer Science and Engineering
Research output
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Contribution to journal
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Article
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peer-review
Overview
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Keyphrases
Graphics Processing Unit
100%
Allocator
100%
Shader Processors
100%
Register Allocation
60%
Embedded Systems
40%
Register Pressure
40%
High Performance
20%
High Energy
20%
Energy Efficiency
20%
Major Components
20%
Energy Management
20%
Four Elements
20%
Computer Graphics
20%
Hardware Resources
20%
Register Packing
20%
Register Spilling
20%
All Elements
20%
Runnable
20%
Access Latency
20%
Shader Programs
20%
Geometric Mean
20%
Register Requirements
20%
Register-based
20%
Unit Design
20%
Shader
20%
General-purpose Computing
20%
Performance Efficiency
20%
Free Element
20%
Element-based
20%
Live Variables
20%
Allocation Framework
20%
Computer Science
Register Allocator
100%
Graphics Processing Unit
100%
Register Allocation
60%
Embedded System
40%
Experimental Result
20%
Energy Efficiency
20%
Major Component
20%
Limiting Factor
20%
Computer Graphic
20%
Hardware Resource
20%
Live Variable
20%