Variable sampling slope (VSS) and no-deadtime ramp generator (NDRG) techniques for closed-loop interleaving power factor correction (PFC) design with suppression of current mismatch
Chun Yen Chen*, Ruei Hong Peng, Jen Chieh Tsai, Yu Chi Kang, Chia Lung Ni, Yi Ting Chen, Ke-Horng Chen, Shih Ming Wang, Ming Wei Lee, Hsin Yu Luo
Research output: Contribution to conference › Paper › peer-review
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