TY - GEN
T1 - Variability Analysis of Stacked-Nanosheet FeFET for MLC Memory and Synapse Applications
AU - Lin, Heng Li
AU - Su, Pin
N1 - Publisher Copyright:
© 2023 JSAP.
PY - 2023
Y1 - 2023
N2 - This work investigates the variability of Stacked-Nanosheet FeFET for scaled NVM, MLC and synapse applications considering the random ferroelectric-dielectric phase distribution with TCAD atomistic simulations. Our study indicates that, by increasing the number of tiers, the variability in threshold voltage of each state, memory window and the synapse conductance response of the Stacked-Nanosheet based ferroelectric devices can all be mitigated without footprint penalty.
AB - This work investigates the variability of Stacked-Nanosheet FeFET for scaled NVM, MLC and synapse applications considering the random ferroelectric-dielectric phase distribution with TCAD atomistic simulations. Our study indicates that, by increasing the number of tiers, the variability in threshold voltage of each state, memory window and the synapse conductance response of the Stacked-Nanosheet based ferroelectric devices can all be mitigated without footprint penalty.
UR - http://www.scopus.com/inward/record.url?scp=85167433106&partnerID=8YFLogxK
U2 - 10.23919/SNW57900.2023.10183975
DO - 10.23919/SNW57900.2023.10183975
M3 - Conference contribution
AN - SCOPUS:85167433106
T3 - 2023 Silicon Nanoelectronics Workshop, SNW 2023
SP - 53
EP - 54
BT - 2023 Silicon Nanoelectronics Workshop, SNW 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th Silicon Nanoelectronics Workshop, SNW 2023
Y2 - 11 June 2023 through 12 June 2023
ER -