Unleash the parallelism of 3DIC partitioning on GPGPU

Hsien Kai Kuo; Bo-Cheng Lai; Jing Yang Jou

doi:10.1109/SOCC.2010.5784745

Unleash the parallelism of 3DIC partitioning on GPGPU

Hsien Kai Kuo^*, Bo-Cheng Lai, Jing Yang Jou

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Taking full advantage of 3DIC technology requires innovative EDA tools that can optimize a multi-layered complex system. However, the optimization algorithms on the multi-layered 3DIC are usually computationally expensive. Parallel computing has been considered as a solution to manage the exploding computational requirement of future EDA tools. This paper proposes PP3D, a parallel 3DIC partitioning algorithm. PP3D enhances the execution speed by exposing the parallelism of FM algorithm. It also coordinates the parallel execution to retain the optimization quality. A design methodology is proposed to streamline the optimization from PP3D algorithm to the underlying GPGPU many-core architecture. The results on the ISPD98 benchmark demonstrate an average of 15X runtime speedup, while the maximum speedup can reach 37X.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2010
Pages	127-132
Number of pages	6
DOIs	https://doi.org/10.1109/SOCC.2010.5784745
State	Published - 1 Dec 2010
Event	23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States Duration: 27 Sep 2010 → 29 Sep 2010

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference	23rd IEEE International SOC Conference, SOCC 2010
Country/Territory	United States
City	Las Vegas, NV
Period	27/09/10 → 29/09/10

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10.1109/SOCC.2010.5784745

Cite this

@inproceedings{85b48521b9c24e519a8b2967af6bf60c,

title = "Unleash the parallelism of 3DIC partitioning on GPGPU",

abstract = "Taking full advantage of 3DIC technology requires innovative EDA tools that can optimize a multi-layered complex system. However, the optimization algorithms on the multi-layered 3DIC are usually computationally expensive. Parallel computing has been considered as a solution to manage the exploding computational requirement of future EDA tools. This paper proposes PP3D, a parallel 3DIC partitioning algorithm. PP3D enhances the execution speed by exposing the parallelism of FM algorithm. It also coordinates the parallel execution to retain the optimization quality. A design methodology is proposed to streamline the optimization from PP3D algorithm to the underlying GPGPU many-core architecture. The results on the ISPD98 benchmark demonstrate an average of 15X runtime speedup, while the maximum speedup can reach 37X.",

author = "Kuo, {Hsien Kai} and Bo-Cheng Lai and Jou, {Jing Yang}",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/SOCC.2010.5784745",

language = "English",

isbn = "9781424466832",

series = "Proceedings - IEEE International SOC Conference, SOCC 2010",

pages = "127--132",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2010",

note = "null ; Conference date: 27-09-2010 Through 29-09-2010",

}

TY - GEN

T1 - Unleash the parallelism of 3DIC partitioning on GPGPU

AU - Kuo, Hsien Kai

AU - Lai, Bo-Cheng

AU - Jou, Jing Yang

PY - 2010/12/1

Y1 - 2010/12/1

N2 - Taking full advantage of 3DIC technology requires innovative EDA tools that can optimize a multi-layered complex system. However, the optimization algorithms on the multi-layered 3DIC are usually computationally expensive. Parallel computing has been considered as a solution to manage the exploding computational requirement of future EDA tools. This paper proposes PP3D, a parallel 3DIC partitioning algorithm. PP3D enhances the execution speed by exposing the parallelism of FM algorithm. It also coordinates the parallel execution to retain the optimization quality. A design methodology is proposed to streamline the optimization from PP3D algorithm to the underlying GPGPU many-core architecture. The results on the ISPD98 benchmark demonstrate an average of 15X runtime speedup, while the maximum speedup can reach 37X.

AB - Taking full advantage of 3DIC technology requires innovative EDA tools that can optimize a multi-layered complex system. However, the optimization algorithms on the multi-layered 3DIC are usually computationally expensive. Parallel computing has been considered as a solution to manage the exploding computational requirement of future EDA tools. This paper proposes PP3D, a parallel 3DIC partitioning algorithm. PP3D enhances the execution speed by exposing the parallelism of FM algorithm. It also coordinates the parallel execution to retain the optimization quality. A design methodology is proposed to streamline the optimization from PP3D algorithm to the underlying GPGPU many-core architecture. The results on the ISPD98 benchmark demonstrate an average of 15X runtime speedup, while the maximum speedup can reach 37X.

UR - http://www.scopus.com/inward/record.url?scp=79960709771&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2010.5784745

DO - 10.1109/SOCC.2010.5784745

M3 - Conference contribution

AN - SCOPUS:79960709771

SN - 9781424466832

T3 - Proceedings - IEEE International SOC Conference, SOCC 2010

SP - 127

EP - 132

BT - Proceedings - IEEE International SOC Conference, SOCC 2010

Y2 - 27 September 2010 through 29 September 2010

ER -

Unleash the parallelism of 3DIC partitioning on GPGPU

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