Unified bit-parallel arithmetic processor using redundant binary representation

Sau-Gee Chen

doi:10.1109/PCCC.1989.37367

Unified bit-parallel arithmetic processor using redundant binary representation

Sau-Gee Chen^*

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

Abstract

An addition rule for signed-digit representation (SDR), generalized from the addition rule of redundant binary representation, is proposed which is free from carry-propagation. The MSD (most significant digit)-first multiplication operation is easily devised by incorporating hardware redundancy with the redundancy in this addition rule. By combing the all MSD-first arithmetic operations, a unified arithmetic processor is obtained which can perform division, multiplication, and square-root operations. This unified processor is similar in structure to an array multiplier. It provides three advantages over the conventional arithmetic unit: (1) higher speed, (2) more functional capability, and (3) better area utilization. It is also suitable for VLSI implementation.

Original language	English
Pages	91-96
Number of pages	6
DOIs	https://doi.org/10.1109/PCCC.1989.37367
State	Published - 22 Mar 1989
Event	Eighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings - Scottsdale, AZ, USA Duration: 22 Mar 1989 → 24 Mar 1989

Conference

Conference	Eighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings
City	Scottsdale, AZ, USA
Period	22/03/89 → 24/03/89

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10.1109/PCCC.1989.37367

Cite this

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Unified bit-parallel arithmetic processor using redundant binary representation

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