Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution

Ming-Dou Ker; Cheng Cheng Yen

doi:10.1109/EMCZUR.2007.4388198

Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution

Ming-Dou Ker^*, Cheng Cheng Yen

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.

Original language	English
Title of host publication	Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC
Pages	69-72
Number of pages	4
DOIs	https://doi.org/10.1109/EMCZUR.2007.4388198
State	Published - 1 Dec 2007
Event	18th International Zurich Symposium on Electromagnetic Compatibility, EMC - Munich, Germany Duration: 24 Sep 2007 → 28 Sep 2007

Publication series

Name	Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC

Conference

Conference	18th International Zurich Symposium on Electromagnetic Compatibility, EMC
Country/Territory	Germany
City	Munich
Period	24/09/07 → 28/09/07

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10.1109/EMCZUR.2007.4388198

Cite this

Ker, M.-D., & Yen, C. C. (2007). Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution. In Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC (pp. 69-72). Article 4388198 (Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC). https://doi.org/10.1109/EMCZUR.2007.4388198

Ker, Ming-Dou ; Yen, Cheng Cheng. / Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution. Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC. 2007. pp. 69-72 (Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC).

@inproceedings{8b1dd2b670e24776a44e83d8cfef03d0,

title = "Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution",

abstract = "Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.",

author = "Ming-Dou Ker and Yen, {Cheng Cheng}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/EMCZUR.2007.4388198",

language = "English",

isbn = "9783952328606",

series = "Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC",

pages = "69--72",

booktitle = "Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC",

note = "18th International Zurich Symposium on Electromagnetic Compatibility, EMC ; Conference date: 24-09-2007 Through 28-09-2007",

}

Ker, M-D & Yen, CC 2007, Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution. in Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC., 4388198, Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC, pp. 69-72, 18th International Zurich Symposium on Electromagnetic Compatibility, EMC, Munich, Germany, 24/09/07. https://doi.org/10.1109/EMCZUR.2007.4388198

Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution. / Ker, Ming-Dou; Yen, Cheng Cheng.
Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC. 2007. p. 69-72 4388198 (Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution

AU - Ker, Ming-Dou

AU - Yen, Cheng Cheng

PY - 2007/12/1

Y1 - 2007/12/1

N2 - Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.

AB - Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.

UR - http://www.scopus.com/inward/record.url?scp=47149100335&partnerID=8YFLogxK

U2 - 10.1109/EMCZUR.2007.4388198

DO - 10.1109/EMCZUR.2007.4388198

M3 - Conference contribution

AN - SCOPUS:47149100335

SN - 9783952328606

T3 - Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC

SP - 69

EP - 72

BT - Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC

T2 - 18th International Zurich Symposium on Electromagnetic Compatibility, EMC

Y2 - 24 September 2007 through 28 September 2007

ER -

Ker MD, Yen CC. Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution. In Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC. 2007. p. 69-72. 4388198. (Proceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC). doi: 10.1109/EMCZUR.2007.4388198

Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution

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