Ultrathin Sub-5-nm Hf1-xZrxO2for a Stacked Gate-all-Around Nanowire Ferroelectric FET with Internal Metal Gate

Shen Yang Lee, Chia Chin Lee, Yi Shan Kuo, Shou Wei Li, Tien Sheng Chao*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


This study investigates a device's ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf1-xZrxO2 (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO2) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using a sub-5-nm HZO and seed layer to fabricate a gate-all-around (GAA) nanowire (NW); a FeFET with a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure; and a double layer (DL) of the channel. The channel size used in the experiment was approximately 9.6times16 nm2 and the total thickness of the gate stack was 9.2 nm. This thickness is 50.5% less than our previous experiment. The FeFET exhibits a considerably high {I}-{on} - {I}-{off} ratio exceeding 107. The IMG serves as a potential equalizer and the ferroelectric material is arranged in a more symmetrical electric field. This results in a lower subthreshold (sub- {V}-{TH} ) swing ( S.S.-{min}= 49.3mV/decade) with a wide range ( 10 {3} ) of drain currentcompared to that without an IMG. The findings indicate that a high-performance GAA FET can be achieved by combining a DL channel, GAA NW, ferroelectric material, and an IMG.

Original languageEnglish
Article number9344700
Pages (from-to)236-241
Number of pages6
JournalIEEE Journal of the Electron Devices Society
StatePublished - 2021


  • FeFET
  • gate-all-around
  • HZO
  • IMG
  • nanowire
  • Poly-Si
  • seed layer
  • Stacked channel


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