Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Po Yen Chiu; Ming-Dou Ker; Fu Yi Tsai; Yeong Jar Chang

doi:10.1109/IRPS.2009.5173343

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Po Yen Chiu^*, Ming-Dou Ker, Fu Yi Tsai, Yeong Jar Chang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

Original language	English
Title of host publication	2009 IEEE International Reliability Physics Symposium, IRPS 2009
Pages	750-753
Number of pages	4
DOIs	https://doi.org/10.1109/IRPS.2009.5173343
State	Published - 2009
Event	2009 IEEE International Reliability Physics Symposium, IRPS 2009 - Montreal, QC, Canada Duration: 26 Apr 2009 → 30 Apr 2009

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Conference

Conference	2009 IEEE International Reliability Physics Symposium, IRPS 2009
Country/Territory	Canada
City	Montreal, QC
Period	26/04/09 → 30/04/09

Keywords

ESD clamp circuit
Electrostatic discharge (ESD)
Gate leakage
Silicon-controlled rectifier (SCR)

Access to Document

10.1109/IRPS.2009.5173343

Cite this

@inproceedings{611c5a787111469c83710a7662ee4f57,

title = "Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process",

abstract = "A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.",

keywords = "ESD clamp circuit, Electrostatic discharge (ESD), Gate leakage, Silicon-controlled rectifier (SCR)",

author = "Chiu, {Po Yen} and Ming-Dou Ker and Tsai, {Fu Yi} and Chang, {Yeong Jar}",

year = "2009",

doi = "10.1109/IRPS.2009.5173343",

language = "English",

isbn = "0780388038",

series = "IEEE International Reliability Physics Symposium Proceedings",

pages = "750--753",

booktitle = "2009 IEEE International Reliability Physics Symposium, IRPS 2009",

note = "2009 IEEE International Reliability Physics Symposium, IRPS 2009 ; Conference date: 26-04-2009 Through 30-04-2009",

}

Chiu, PY, Ker, M-D, Tsai, FY & Chang, YJ 2009, Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process. in 2009 IEEE International Reliability Physics Symposium, IRPS 2009., 5173343, IEEE International Reliability Physics Symposium Proceedings, pp. 750-753, 2009 IEEE International Reliability Physics Symposium, IRPS 2009, Montreal, QC, Canada, 26/04/09. https://doi.org/10.1109/IRPS.2009.5173343

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process. / Chiu, Po Yen; Ker, Ming-Dou; Tsai, Fu Yi et al.
2009 IEEE International Reliability Physics Symposium, IRPS 2009. 2009. p. 750-753 5173343 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

AU - Chiu, Po Yen

AU - Ker, Ming-Dou

AU - Tsai, Fu Yi

AU - Chang, Yeong Jar

PY - 2009

Y1 - 2009

N2 - A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

AB - A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

KW - ESD clamp circuit

KW - Electrostatic discharge (ESD)

KW - Gate leakage

KW - Silicon-controlled rectifier (SCR)

UR - http://www.scopus.com/inward/record.url?scp=70449102619&partnerID=8YFLogxK

U2 - 10.1109/IRPS.2009.5173343

DO - 10.1109/IRPS.2009.5173343

M3 - Conference contribution

AN - SCOPUS:70449102619

SN - 0780388038

SN - 9780780388031

T3 - IEEE International Reliability Physics Symposium Proceedings

SP - 750

EP - 753

BT - 2009 IEEE International Reliability Physics Symposium, IRPS 2009

T2 - 2009 IEEE International Reliability Physics Symposium, IRPS 2009

Y2 - 26 April 2009 through 30 April 2009

ER -

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this