Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology

Federico A. Altolaguirre; Ming-Dou Ker

doi:10.1109/VLDI-DAT.2013.6533866

Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology

Federico A. Altolaguirre, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

The gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25°C, and a ESD robustness of 3kV HBM and 200V MM.

Original language	English
Title of host publication	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs	https://doi.org/10.1109/VLDI-DAT.2013.6533866
State	Published - 15 Aug 2013
Event	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan Duration: 22 Apr 2013 → 24 Apr 2013

Publication series

Name	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Conference

Conference	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/13 → 24/04/13

Access to Document

10.1109/VLDI-DAT.2013.6533866

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title = "Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology",

abstract = "The gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25°C, and a ESD robustness of 3kV HBM and 200V MM.",

author = "Altolaguirre, {Federico A.} and Ming-Dou Ker",

year = "2013",

month = aug,

day = "15",

doi = "10.1109/VLDI-DAT.2013.6533866",

language = "English",

isbn = "9781467344357",

series = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

booktitle = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

note = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 ; Conference date: 22-04-2013 Through 24-04-2013",

}

Altolaguirre, FA & Ker, M-D 2013, Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. in 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013., 6533866, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, 22/04/13. https://doi.org/10.1109/VLDI-DAT.2013.6533866

Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. / Altolaguirre, Federico A.; Ker, Ming-Dou.
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533866 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - The gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25°C, and a ESD robustness of 3kV HBM and 200V MM.

AB - The gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25°C, and a ESD robustness of 3kV HBM and 200V MM.

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DO - 10.1109/VLDI-DAT.2013.6533866

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SN - 9781467344357

T3 - 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

BT - 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

T2 - 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Y2 - 22 April 2013 through 24 April 2013

ER -

Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology

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