U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory

Ming Hung Wu*, Ming Chun Hong, Ching Shih, Yao Jen Chang, Yu Chen Hsin, Shih Ching Chiu, Kuan Ming Chen, Yi Hui Su, Chih Yao Wang, Shan Yi Yang, Guan Long Chen, Hsin Han Lee, Sk Ziaur Rahaman, I. Jung Wang, Chen Yi Shih, Tsun Chun Chang, Jeng Hua Wei, Shyh Shyuan Sheu, Wei Chung Lo, Shih Chieh ChangTuo Hung Hou*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

U-MRAM, an enabler of a diode-selected cross-point MRAM array, is demonstrated using a mature device structure identical to STT-MRAM. U-MRAM exploits the probabilistic switching of thermal fluctuations using a single write voltage. The asymmetric synthetic antiferromagnetic layer (SAF) enables promising UMRAM properties, including low voltage (0.6 V), high speed (10 ns), excellent endurance (> 10 10), and long retention (>10 years) without an external magnetic field. Diode-selected U-MRAM is a strong candidate for future high-density embedded memory.

Original languageEnglish
Title of host publication2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863488069
DOIs
StatePublished - 2023
Event2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
Duration: 11 Jun 202316 Jun 2023

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2023-June
ISSN (Print)0743-1562

Conference

Conference2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/TerritoryJapan
CityKyoto
Period11/06/2316/06/23

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