Two-level FIFO buffer design for routers in on-chip interconnection networks

Keyphrases

• Router 100%
• Two-level 100%
• First-in-first-out 100%
• Buffer Design 100%
• On-chip Interconnection Networks 100%
• Buffer Architecture 100%
• Virtual Channel 33%
• High Performance 16%
• Power Reduction 16%
• Power Consumption 16%
• Area Consumption 16%
• 65nm CMOS 16%
• System-on-chip Design 16%
• Buffer Size 16%
• Multiple Access 16%
• Shared Buffer 16%
• Storage Elements 16%
• Integrated Solutions 16%
• Work Analysis 16%

Computer Science

• First-in-First-Out 100%
• Interconnection Network 100%
• Virtual Channel 33%
• Power Consumption 16%
• Multiple Access 16%
• Storage Element 16%
• Integrated Solution 16%
• Performance Router 16%
• System-on-Chip 16%