TY - BOOK
T1 - Turbo decoder architecture for beyond-4G applications
AU - Wong, Cheng Chi
AU - Chang, Hsie-Chia
N1 - Publisher Copyright:
© 2014 Springer Science+Business Media New York. All rights are reserved.
PY - 2014/10/1
Y1 - 2014/10/1
N2 - This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.
AB - This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.
UR - http://www.scopus.com/inward/record.url?scp=84929669708&partnerID=8YFLogxK
U2 - 10.1007/978-1-4614-8310-6
DO - 10.1007/978-1-4614-8310-6
M3 - Book
AN - SCOPUS:84929669708
SN - 1461483093
SN - 9781461483090
VL - 9781461483106
BT - Turbo decoder architecture for beyond-4G applications
PB - Springer New York
ER -