TSV Integration with Chip Level TSV-to-Pad Cu/SiO2 Hybrid Bonding for DRAM Multiple Layer Stacking

Tzu Heng Hung, James Yi Jen Lo, Tzu Ying Kuo, Shing Yih Shih, Sheng Fu Huang, Yen Ling Lin, Hsih Yang Chiu, Wei Zhong Li, Han Wen Hu, Hsiang Hung Chang, Chiang Lin Shih, Jeff J.P. Lin, Kuan Neng Chen

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

55 μm depth TSV-to-pad Cu/SiO2 hybrid bonding for the integration of Si interposer and DRAM has been demonstrated by room temperature bonding and an annealing process. Optimization of surface pretreatment is the key to bonding of Cu and SiO2 with high quality at the same time. In addition, the TSV protrusion issue, which would cause failure of multiple layer stacking, was effectively improved by Cu grain stabilization process and pre-treatment adjustment. The electrical measurements were performed, showing the low and stable TSV resistance. Thus, the TSV-to-pad hybrid bonding with no μ-bumps is promising for further scaling and stacking in HBM or chiplet integration scenarios.

Original languageEnglish
Pages (from-to)1
Number of pages1
JournalIeee Electron Device Letters
DOIs
StateAccepted/In press - 2023

Keywords

  • 3DIC
  • Annealing
  • Bonding
  • DRAM integration
  • hybrid bonding
  • Plasma temperature
  • Plasmas
  • Stacking
  • Surface treatment
  • Through-silicon vias
  • TSV bonding

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