Trapping/Detrapping Kinetic Modeling under Positive/Negative Gate Stress Including Inhibition Dynamics in 4H-SiC MOS Capacitors

Incorporating inhibition dynamics for the first time, in this work, we successfully model the trapping and detrapping kinetics under positive and negative bias stress in 4H-SiC MOS-capacitors. The positive/negative gate bias stress is applied during extended measure stress measure (eMSM)-fast C-V measurements, demonstrating noticeable trapping/detrapping dynamics. Analytical expressions based on the inhibition mechanism are developed to successfully model the trapping/detrapping phenomenon and estimate the location of the trap, which is found to be 1 nm from the dielectric/SiC interface due to border/interface traps. The developed analytical model can provide valuable insights in understanding positive/negative bias instability in SiC technology.