Transient-induced latchup in CMOS technology: Physical mechanism and device simulation

Ming-Dou Ker*, Sheng Fu Hsu

*Corresponding author for this work

    Research output: Contribution to journalConference articlepeer-review

    9 Scopus citations

    Abstract

    The physical mechanism of transient-induced latchup (TLU) in CMOS ICs has been clearly characterized by device simulation and experimental verification in time domain perspective. An underdamped sine-wave-like voltage has been clarified as the real TLU-triggering stimulus under system-level electrostatic discharge (ESD) test. The specific "sweep-back" current caused by the minority carriers stored within the pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU.

    Original languageEnglish
    Pages (from-to)937-940
    Number of pages4
    JournalTechnical Digest - International Electron Devices Meeting, IEDM
    DOIs
    StatePublished - 2004
    EventIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
    Duration: 13 Dec 200415 Dec 2004

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