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Transient-Induced Latchup in CMOS Integrated Circuits
Ming-Dou Ker
*
, Sheng Fu Hsu
*
Corresponding author for this work
Research output
:
Book/Report
›
Book
›
peer-review
40
Scopus citations
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Keyphrases
Latch-up
100%
CMOS Integrated Circuits
100%
IC Design
50%
Layout Rule
50%
Physical Mechanism
33%
Failure Analysis
33%
System-level ESD Test
33%
Practicing Engineers
33%
CMOS Process
16%
CMOS Technology
16%
Circuit Design
16%
System Design
16%
Layout Area
16%
Design House
16%
CMOS Circuit Design
16%
Time to Market
16%
IC chip
16%
Area-efficient
16%
Semiconductor Devices
16%
Design Errors
16%
Induced Failures
16%
Design Analysis
16%
Design Management
16%
CMOS IC
16%
Component Level
16%
Undergraduate Students
16%
High-density chip
16%
Management Application
16%
O-cell
16%
Design Application
16%
Circuit Layout
16%
Application Error
16%
Compact Layout
16%
Circuit Failure
16%
Measurement Setup
16%
Industry Problems
16%
Experimental Methodology
16%
Chip Layout
16%
Management System Design
16%
EFT Test
16%
Application Reliability
16%
Application Design
16%
Postgraduate Students
16%
Design Reliability Analysis
16%
Real-world Experience
16%
IC Layout
16%
Engineering
Transients
100%
Integrated Circuit Design
100%
CMOS Integrated Circuits
100%
Circuit Design
66%
Design Analysis
66%
Failure Analysis
66%
Induced Failure
33%
Semiconductor Device
33%
Component Level
33%
Integrated Circuit Layout
33%
Measurement Setup
33%
Chip Layout
33%
Postgraduate Student
33%