TY - GEN
T1 - Transient-induced latchup in CMOS integrated circuits due to Electrical Fast Transient (EFT) test
AU - Yen, Cheng Cheng
AU - Ker, Ming-Dou
PY - 2007/12/1
Y1 - 2007/12/1
N2 - The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified With the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-∝m CMOS technology.
AB - The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified With the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-∝m CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=39749147788&partnerID=8YFLogxK
U2 - 10.1109/IPFA.2007.4378095
DO - 10.1109/IPFA.2007.4378095
M3 - Conference contribution
AN - SCOPUS:39749147788
SN - 1424410142
SN - 9781424410149
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
SP - 253
EP - 256
BT - Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
T2 - 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
Y2 - 11 July 2007 through 13 July 2007
ER -