Transient-induced latchup in CMOS ICs under electrical fast-transient test

Cheng Cheng Yen*, Ming-Dou Ker, Tung Yang Chen

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    18 Scopus citations


    The occurrence of transient-induced latchup (TLU) in CMOS integrated circuits (ICs) under electrical fast-transient (EFT) tests is studied. The test chip with the parasitic silicon-controlled-rectifier (SCR) structure fabricated by a 0.18-μ m CMOS process was used in EFT tests. For physical mechanism characterization, the specific swept-back current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is the major cause of TLU under EFT tests. Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under EFT tests. By choosing the proper components in each noise filter network, the TLU immunity of CMOS ICs against EFT tests can be greatly improved.

    Original languageEnglish
    Article number4799110
    Pages (from-to)255-264
    Number of pages10
    JournalIEEE Transactions on Device and Materials Reliability
    Issue number2
    StatePublished - Jun 2009


    • Board-level noise filter
    • Electrical fast transient (EFT)
    • Latchup
    • Silicon-controlled rectifier (SCR)
    • Transient-induced latchup (TLU)


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