Abstract
The bipolar (underdamped sinusoidal) transient noise on power pins of CMOS integrated circuits (ICs) can trigger latchup in CMOS ICs under system-level electrostatic-discharge test. Two dominant parameters of bipolar transient noise-damping frequency and damping factor-strongly depend on system shielding, board-level noise filter, chip-/board-level layout, etc. The transient-induced-latchup (TLU) dependence on power-pin damping frequency and damping factor was characterized by device simulation and verified by experimental measurement. From the simulation results, bipolar-trigger waveforms with damping frequencies of several tens of megahertz can trigger the TLU most easily. However, TLU is less sensitive to the bipolar-trigger waveforms with an excessively large damping factor or an excessively low/high damping frequency. The simulation results have been experimentally verified with the silicon-controlled-rectifier (SCR) test structures that are fabricated in a 0.25-μm CMOS technology.
| Original language | English |
|---|---|
| Pages (from-to) | 2002-2010 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 54 |
| Issue number | 8 |
| DOIs | |
| State | Published - 1 Aug 2007 |
Keywords
- Bipolar-trigger voltage
- Latchup
- Silicon-controlled rectifier (SCR)
- System-level electrostatic-discharge (ESD) test
- Transient-induced latchup (TLU)