Throughput optimization for latency-insensitive system with minimal queue insertion

Keyphrases

• Throughput Optimization 100%
• Latency-sensitive 100%
• Interconnect Delay 50%
• System Throughput 25%
• Latency 25%
• Large Systems 25%
• Fabrication Methods 25%
• System-on-chip Design 25%
• Deep Submicron Technology 25%
• Optimization Techniques 25%
• Critical Performance 25%
• Back Pressure 25%
• Integer Linear Programming 25%
• Global Interconnect 25%
• Multicycle Communication 25%
• IP Core 25%
• Performance Obstacles 25%
• Queue Size 25%

Computer Science

• Interconnect Delay 100%
• Experimental Result 50%
• Optimization Technique 50%
• Integer-Linear Programming 50%
• System-on-Chip 50%