Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

Ya Shih Huang; Juinn-Dar Huang

doi:10.1109/ASQED.2010.5548228

Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

Ya Shih Huang^*, Juinn-Dar Huang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing- based scheme.

Original language	English
Title of host publication	Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010
Pages	134-139
Number of pages	6
DOIs	https://doi.org/10.1109/ASQED.2010.5548228
State	Published - 17 Sep 2010
Event	2nd Asia Symposium on Quality Electronic Design, ASQED 2010 - Penang, Malaysia Duration: 3 Aug 2010 → 4 Aug 2010

Publication series

Name	Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010

Conference

Conference	2nd Asia Symposium on Quality Electronic Design, ASQED 2010
Country/Territory	Malaysia
City	Penang
Period	3/08/10 → 4/08/10

Keywords

Multicycle communication
Partition-based placement
Regular distributed architecture
Throughput-driven

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10.1109/ASQED.2010.5548228

Cite this

Huang, Y. S., & Huang, J.-D. (2010). Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture. In Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010 (pp. 134-139). Article 5548228 (Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010). https://doi.org/10.1109/ASQED.2010.5548228

@inproceedings{cba1b1d918dc4f2f989e6cbafc7b57c6,

title = "Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture",

abstract = "As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing- based scheme.",

keywords = "Multicycle communication, Partition-based placement, Regular distributed architecture, Throughput-driven",

author = "Huang, {Ya Shih} and Juinn-Dar Huang",

year = "2010",

month = sep,

day = "17",

doi = "10.1109/ASQED.2010.5548228",

language = "English",

isbn = "9781424478088",

series = "Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010",

pages = "134--139",

booktitle = "Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010",

note = "2nd Asia Symposium on Quality Electronic Design, ASQED 2010 ; Conference date: 03-08-2010 Through 04-08-2010",

}

Huang, YS & Huang, J-D 2010, Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture. in Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010., 5548228, Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010, pp. 134-139, 2nd Asia Symposium on Quality Electronic Design, ASQED 2010, Penang, Malaysia, 3/08/10. https://doi.org/10.1109/ASQED.2010.5548228

Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture. / Huang, Ya Shih; Huang, Juinn-Dar.
Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010. 2010. p. 134-139 5548228 (Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Huang, Juinn-Dar

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N2 - As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing- based scheme.

AB - As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based partitioning paradigm and is capable of keeping near-critical loops as physically close as possible to maximize system throughput. The experimental results show that the proposed placer achieves 4.57 times throughput improvement compared with a well-known simulated-annealing- based scheme.

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T3 - Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010

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BT - Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010

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Throughput-driven hierarchical placement for two-dimensional regular multicycle communication architecture

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