Copper (Cu) interconnects are one of promising approaches for design and fabrication of gigascale ultra-large scale integrated (ULSI) circuit. In this paper, three configurations of interconnect, the parallel lines, the parallel lines on a plane, and the parallel lines between two planes are investigated. Three-dimensional simulation is performed by solving an electrostatic model using adaptive computing technique. For the studied three configurations, delay of resistance and capacitance (RC) is calculated with respect to different line spacing, line distance to plane, line width, and line height. Equivalent circuit is implemented for circuit simulation, and calculation of timing delay and crosstalk. It is found that RC time constant not only depends on the configurations but also dominates by the ratio of line height to line width. For sub-100 nm fabrication technology, there is an optimal design with respect to the three configurations. If the ratio of line height to line width is larger than 1, the RC time constant reaches to a minimum.