Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video

Chih Yuan Chang; Po-Tsang Huang; Yi Chun Chen; Tian-Sheuan Chang; Wei Hwang

doi:10.1109/SOCC.2014.6948903

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video

Chih Yuan Chang, Po-Tsang Huang, Yi Chun Chen, Tian-Sheuan Chang, Wei Hwang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.

Original language	English
Title of host publication	International System on Chip Conference
Editors	Kaijian Shi, Thomas Buchner, Danella Zhao, Ramalingam Sridhar
Publisher	IEEE Computer Society
Pages	76-81
Number of pages	6
ISBN (Electronic)	9781479933785
DOIs	https://doi.org/10.1109/SOCC.2014.6948903
State	Published - 5 Nov 2014
Event	27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States Duration: 2 Sep 2014 → 5 Sep 2014

Publication series

Name	International System on Chip Conference
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	27th IEEE International System on Chip Conference, SOCC 2014
Country/Territory	United States
City	Las Vegas
Period	2/09/14 → 5/09/14

Access to Document

10.1109/SOCC.2014.6948903

Cite this

Chang, C. Y., Huang, P.-T., Chen, Y. C., Chang, T.-S., & Hwang, W. (2014). Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. In K. Shi, T. Buchner, D. Zhao, & R. Sridhar (Eds.), International System on Chip Conference (pp. 76-81). Article 6948903 (International System on Chip Conference). IEEE Computer Society. https://doi.org/10.1109/SOCC.2014.6948903

@inproceedings{69b0840fd1774dd7951120271216152c,

title = "Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video",

abstract = "With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.",

author = "Chang, {Chih Yuan} and Po-Tsang Huang and Chen, {Yi Chun} and Tian-Sheuan Chang and Wei Hwang",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 27th IEEE International System on Chip Conference, SOCC 2014 ; Conference date: 02-09-2014 Through 05-09-2014",

year = "2014",

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doi = "10.1109/SOCC.2014.6948903",

language = "English",

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Chang, CY, Huang, P-T, Chen, YC, Chang, T-S & Hwang, W 2014, Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. in K Shi, T Buchner, D Zhao & R Sridhar (eds), International System on Chip Conference., 6948903, International System on Chip Conference, IEEE Computer Society, pp. 76-81, 27th IEEE International System on Chip Conference, SOCC 2014, Las Vegas, United States, 2/09/14. https://doi.org/10.1109/SOCC.2014.6948903

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. / Chang, Chih Yuan; Huang, Po-Tsang; Chen, Yi Chun et al.
International System on Chip Conference. ed. / Kaijian Shi; Thomas Buchner; Danella Zhao; Ramalingam Sridhar. IEEE Computer Society, 2014. p. 76-81 6948903 (International System on Chip Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hwang, Wei

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N2 - With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.

AB - With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.

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Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video

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