Abstract
This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics of highly-scaled tri-gate n-MOSFETs with InGaAs channel based on ITRS 2021 technology node through numerical simulation corroborated with theoretical calculation. This paper indicates that, when studying short-channel effects in III-V FETs, one has to account for quantum-confinement, or else predictions will be pessimistic. Due to 2-D quantum-confinement, the DIBL of the InGaAs tri-gate devices can be significantly suppressed and be comparable to the Si counterpart. Besides, for highly-scaled InGaAs tri-gate NFETs, the impact of buried-oxide thickness on DIBL becomes minor, and the DIBL sensitivity to the fin-width and gate-length variations can also be suppressed by the quantum-confinement effect. This paper may provide insights for tri-gate device design using III-V high-mobility channel materials.
| Original language | English |
|---|---|
| Article number | 7744544 |
| Pages (from-to) | 45-52 |
| Number of pages | 8 |
| Journal | IEEE Journal of the Electron Devices Society |
| Volume | 5 |
| Issue number | 1 |
| DOIs | |
| State | Published - Jan 2017 |
Keywords
- III-V channel
- drain-induced barrier lowering (DIBL)
- process variation
- quantum confinement
- tri-gate MOSFET