TY - GEN
T1 - The wonderful world of designer Ge quantum dots
AU - Wang, I. Hsiang
AU - Hong, Po Yu
AU - Peng, Kang Ping
AU - Lin, Horng Chih
AU - George, Thomas
AU - Li, Pei Wen
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/12/12
Y1 - 2020/12/12
N2 - Starting with our remarkable discovery of spherical germanium (Ge) quantum dot (QD) formation, we have embarked on an exciting journey of further discovery, all the while maintaining CMOS-compatible processes. We have taken advantage of the many peculiar and symbiotic interactions of Si, Ge and O interstitials to create a novel portfolio of electronic, photonic and quantum computing devices. This paper summarizes several of these completely new and counter-intuitive accomplishments. Using a coordinated combination of lithographic patterning and self-assembly, size-tunable spherical Ge QDs were controllably placed at designated spatial locations within Si-containing layers. We exploited the exquisite control available through the thermal oxidation of Si1-xGex patterned structures in proximity to Si3N4/Si layers. Our so-called "designer"Ge QDs have succeeded in opening up myriad device possibilities, including paired QDs for qubits, single-hole transistors (SHTs) for charge sensing, photodetectors and light-emitters for Si photonics, and junctionless (JL) FETs using standard Si processing.
AB - Starting with our remarkable discovery of spherical germanium (Ge) quantum dot (QD) formation, we have embarked on an exciting journey of further discovery, all the while maintaining CMOS-compatible processes. We have taken advantage of the many peculiar and symbiotic interactions of Si, Ge and O interstitials to create a novel portfolio of electronic, photonic and quantum computing devices. This paper summarizes several of these completely new and counter-intuitive accomplishments. Using a coordinated combination of lithographic patterning and self-assembly, size-tunable spherical Ge QDs were controllably placed at designated spatial locations within Si-containing layers. We exploited the exquisite control available through the thermal oxidation of Si1-xGex patterned structures in proximity to Si3N4/Si layers. Our so-called "designer"Ge QDs have succeeded in opening up myriad device possibilities, including paired QDs for qubits, single-hole transistors (SHTs) for charge sensing, photodetectors and light-emitters for Si photonics, and junctionless (JL) FETs using standard Si processing.
UR - http://www.scopus.com/inward/record.url?scp=85102922669&partnerID=8YFLogxK
U2 - 10.1109/IEDM13553.2020.9372027
DO - 10.1109/IEDM13553.2020.9372027
M3 - Conference contribution
AN - SCOPUS:85102922669
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 38.1.1-38.1.4
BT - 2020 IEEE International Electron Devices Meeting, IEDM 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 66th Annual IEEE International Electron Devices Meeting, IEDM 2020
Y2 - 12 December 2020 through 18 December 2020
ER -