TY - GEN
T1 - The SMEM Seeding Acceleration for DNA Sequence Alignment
AU - Chang, Mau-Chung
AU - Chen, Yu Ting
AU - Cong, Jason
AU - Huang, Po-Tsang
AU - Kuo, Chun Liang
AU - Yu, Cody Hao
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/8/16
Y1 - 2016/8/16
N2 - The advance of next-generation sequencing technology has dramatically reduced the cost of genome sequencing. However, processing and analyzing huge amounts of data collected from sequencers introduces significant computation challenges, these have become the bottleneck in many research and clinical applications. For such applications, read alignment is usually one of the most compute-intensive steps. Billions of reads generated from the sequencer need to be aligned to the long reference genome. Recent state-of-the-art software read aligners follow the seed-andextend model. In this paper we focus on accelerating the first seeding stage, which generates the seeds using the supermaximal exact match (SMEM) seeding algorithm. The two main challenges for accelerating this process are 1) how to process a huge number of short reads with high throughput, and 2) how to hide the frequent and long random memory access when we try to fetch the value of the reference genome. In this paper, we propose a scalable array-based architecture, which is composed by many processing engines (PEs) to process large amounts of data simultaneously for the demand of high throughput. Furthermore, we provide a tight software/hardware integration that realizes the proposed architecture on the Intel-Altera HARP system. With a 16-PE accelerator engine, we accelerate the SMEM algorithm by 4x, and the overall SMEM seeding stage by 26% when compared with 16-thread CPU execution. We further analyze the performance bottleneck of the design due to extensive DRAM accesses and discuss the possible improvements that are worthwhile to be explored in the future.
AB - The advance of next-generation sequencing technology has dramatically reduced the cost of genome sequencing. However, processing and analyzing huge amounts of data collected from sequencers introduces significant computation challenges, these have become the bottleneck in many research and clinical applications. For such applications, read alignment is usually one of the most compute-intensive steps. Billions of reads generated from the sequencer need to be aligned to the long reference genome. Recent state-of-the-art software read aligners follow the seed-andextend model. In this paper we focus on accelerating the first seeding stage, which generates the seeds using the supermaximal exact match (SMEM) seeding algorithm. The two main challenges for accelerating this process are 1) how to process a huge number of short reads with high throughput, and 2) how to hide the frequent and long random memory access when we try to fetch the value of the reference genome. In this paper, we propose a scalable array-based architecture, which is composed by many processing engines (PEs) to process large amounts of data simultaneously for the demand of high throughput. Furthermore, we provide a tight software/hardware integration that realizes the proposed architecture on the Intel-Altera HARP system. With a 16-PE accelerator engine, we accelerate the SMEM algorithm by 4x, and the overall SMEM seeding stage by 26% when compared with 16-thread CPU execution. We further analyze the performance bottleneck of the design due to extensive DRAM accesses and discuss the possible improvements that are worthwhile to be explored in the future.
KW - BWA-MEM
KW - FPGA
KW - Intel HARP
KW - PE-array architecture
KW - Supermaximal exact match
KW - read alignment
UR - http://www.scopus.com/inward/record.url?scp=84987638674&partnerID=8YFLogxK
U2 - 10.1109/FCCM.2016.21
DO - 10.1109/FCCM.2016.21
M3 - Conference contribution
AN - SCOPUS:84987638674
T3 - Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016
SP - 32
EP - 39
BT - Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016
Y2 - 1 May 2016 through 3 May 2016
ER -