@inproceedings{41d7259cebbb4189bb8804e523ce7873,
title = "The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate",
abstract = "The selection of the gate dielectric is one of the most critical stability issues in recessed gate AlGaN/GaN transistors. In this work, we show that the quality of the gate dielectric has a strong impact on: 1) the threshold voltage (VTH) hysteresis, 2) the drain current reduction for enhancement mode devices, and 3) the forward gate bias TDDB (time dependent dielectric breakdown). It will be shown that the VTH hysteresis and the current reduction can be minimized by using a dielectric with lower interface state density (Dit) and less border traps, e.g., a PE-ALD SiN dielectric. Furthermore, the 0.01% failures at 20 years TDDB requirement at 150°C for a large power device, e.g., gate width Wg=36mm, necessitates the use of at least a 25nm-thick PE-ALD SiN gate dielectric.",
keywords = "AlGaN/GaN, border traps, depletion mode, enhacement mode, gate dielectric, interface states, PE-ALD SiN, recessed gate",
author = "Tian-Li Wu and Denis Marcon and {De Jaeger}, Brice and {Van Hove}, Marleen and Benoit Bakeroot and Dennis Lin and Steve Stoffels and Xuanwu Kang and Robin Roelofs and Guido Groeseneken and Stefaan Decoutere",
year = "2015",
month = jun,
day = "12",
doi = "10.1109/ISPSD.2015.7123430",
language = "English",
series = "Proceedings of the International Symposium on Power Semiconductor Devices and ICs",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "225--228",
booktitle = "2015 IEEE 27th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015",
address = "美國",
note = "27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015 ; Conference date: 10-05-2015 Through 14-05-2015",
}